New NSF Center Targets Reconfigurable Computing
Under the auspices of the highly acclaimed program for Industry/University Cooperative Research Centers (I/UCRC) at the National Science Foundation (NSF), the Center for High-Performance Reconfigurable Computing (CHREC, pronounced “shreck”) is a new national center and consortium for fundamental research in reconfigurable computing. CHREC is comprised of approximately two-dozen (and growing) organizations from academia, industry, and government with synergistic interests and goals in this field. Having recently completed a two-year development, review, and selection process at NSF, CHREC becomes operational in January 2007.
Recently we got the opportunity to ask Dr. Alan George, the CHREC director, to explain the significance of the new NSF center and help us understand the type of work that will be performed there.
HPCwire: What is the focus of the work at CHREC?
George: High-performance reconfigurable computing, the focus of CHREC, holds tremendous promise in addressing the needs of a broad range of applications, in areas such as signal and image processing, cryptology, communications processing, data and text mining, optimization, bioinformatics, and complex system simulations. Reconfigurable systems span a variety of platform types, from leading-edge machines on earth to mission-critical machines in space. Advantages from a reconfigurable approach can be realized in terms of performance, power, size, cooling, cost, versatility, scalability, and dependability to name a few important facets where conventional computing infrastructure alone is proving unable to meet the needs of an increasing number of critical applications. Preliminary thrust areas for CHREC include device and core building blocks, reconfigurable systems and services, design automation and programming methods and tools, and reconfigurable and parallel algorithms and applications. Research projects in these areas are formulated on an annual basis in concert with Center partners, emphasizing a keen interest in exploring and evaluating new methods as well as key tradeoff analyses.
HPCwire: What are the main goals of CHREC?
George: A broad range of goals have been defined with NSF for CHREC, including: (1) Establish the nation's first multidisciplinary research center in reconfigurable high-performance computing as a basis for long-term partnership and collaboration amongst industry, academe, and government; (2) Directly support the research needs of industry and government partners in a cost-effective manner with pooled, leveraged resources and maximized synergy; (3) Enhance the educational experience for a diverse set of high-quality graduate and undergraduate students; and (4) Advance the knowledge and technologies in this emerging field and ensure relevance of the research with rapid and effective technology transfer.
HPCwire: Why is the field of reconfigurable computing so important to HPC?
George: Although a relatively new field, reconfigurable computing (RC) has come to the forefront as an important processing paradigm for HPC, often in concert with conventional microprocessor-based computing. With RC, the full potential of underlying electronics in a system may be better realized in an adaptive manner. At the heart of RC, field-programmable hardware in its many forms has the potential to revolutionize the performance and efficiency of systems for HPC as well as deployable systems in high-performance embedded computing (HPEC). One ideal of the RC paradigm is to achieve the performance, scalability, power, and cooling advantages of the “Master of a trade,” custom hardware, with the versatility, flexibility, and efficacy of the “Jack of all trades,” a general-purpose processor. As is commonplace with components for HPC, such as microprocessors, memory, networking, storage, etc., critical technologies for RC can also be leveraged from other IT markets to achieve a better performance-cost ratio, most notably the field-programmable gate array or FPGA. Each of these devices is inherently heterogeneous, being a predefined mixture of configurable logic cells and powerful, fixed resources.
HPCwire: What do you think are the biggest opportunities and challenges in this area?
George: Many opportunities and challenges exist in realizing the full potential of reconfigurable hardware for HPC. Among the opportunities offered by field-programmable hardware are a high degree of on-chip parallelism that can be mapped directly from dataflow characteristics of the application's defining parallel algorithm, user control over low-level resource definition and allocation, and user-defined data format and precision rendered efficiently in hardware. In realizing these opportunities, there are many vertical challenges, where we seek to bridge the semantic gap between the high level at which HPC applications are developed and the low level (i.e. HDL) at which hardware is typically defined. There are also many horizontal challenges, where we seek to integrate or marry diverse resources such as microprocessors, FPGAs, and memory in optimal relationships, in essence bridging the paradigm gap between conventional and reconfigurable processing at various levels in the system and software architectures.
Success is expected to come from both revolutionary and evolutionary advances. For example, at one end of the spectrum, internal design strategies of field-programmable devices need to be reevaluated in light of a broad range of HPC and HPEC applications, not only to potentially achieve a more effective mixture of on-chip fixed resources alongside reconfigurable logic blocks, but also as a prime target for higher-level programming and translation. At the other end of the spectrum, new concepts and tools are needed to analyze the algorithmic basis of applications under study (that is, inherent control-flow versus data-flow components, numeric format versus dynamic range), and new programming models to render this basis in an abstracted design strategy, so as to potentially target and exploit a combination of resources (that is, general-purpose processors, reconfigurable processors, and special-purpose processors such as GPUs, DSPs, and NPs). While attempting to build highly heterogeneous systems composed of resources from many diverse categories can be cost-prohibitive, and a goal of uni-paradigm application design for multi-paradigm computing may be extremely difficult to perfect, one of the inherent advantages of RC is that it promises to support these goals in a more flexible and cost-effective manner. Between the two extremes of devices and programming models for multi-paradigm computing, many challenges await with new concepts and tools – compilers, core libraries, system services, debug and performance analysis tools, etc. These and related steps will be of paramount importance for the transition of RC technologies into the mainstream of HPC.
HPCwire: Who are the current participants in CHREC?
George: The lead academic institution for CHREC is the University of Florida, with partner institution at the George Washington University, and pending partner institutions at Virginia Tech and Brigham Young University. Government and industry research partners are of vital importance for all NSF centers. At CHREC, along with the National Science Foundation, founding members include the National Security Agency, NASA Goddard Space Flight Center, Honeywell, Air Force Research Lab, Smiths Aerospace, Rockwell Collins, IBM Research, Oak Ridge National Lab, Sandia National Labs, Office of Naval Research, NASA Marshall Space Flight Center, NASA Langley Research Center, Arctic Region Supercomputer Center, SGI, HP, Intel, and Linux Networx.
HPCwire: How do these industry and government groups participate and benefit?
George: Through participation as research partners in the Center, industry and government members directly benefit in terms of research achievement and technology transfer with a leveraged and synergistic funding pool, collaboration and cooperation with other members, and access to a strong cadre of faculty members, graduate students, and post-doctoral researchers. CHREC members have influence over and access to a broad range of cost-effective research activities at the leading edge of this important new field. They select the project topics that their resources will support and review project progress and results on a semiannual formal basis and continual informal basis and thus benefit from research results in a timely fashion, before new developments lead to publications, with full access to all intellectual property emerging from the Center. Members leverage strong university research labs with world-class facilities. In addition to work conducted in the Center, many benefits arise between members from their memberships, such as new industrial partnerships and teaming opportunities. Recruitment is also a major advantage of participation in CHREC, leveraging interactions with many bright and highly educated and skilled students.
HPCwire: How is CHREC being funded?
George: Per NSF guidelines, industry and government contributions in the form of annual CHREC membership fees, coupled with baseline funds from NSF, university matching funds, and product donations from vendor partners, directly support the operations of the Center in terms of various costs for personnel, equipment, travel, and supplies. Membership fees provide the requisite funds to support the Center's graduate students on a one-to-one basis, and thus the size of the annual membership fee is directly proportional to the cost of supporting one graduate student, while NSF and university funds support various other costs of operation. Multiple annual memberships may be contributed by any organization that wishes to support multiple students and/or projects. The total operating budget for CHREC is projected to approach $2 million per year, in an academic environment that is extremely cost-effective. Thus, a single membership — $35K per year — is an exceptional value. It represents less than two percent of the projected annual budget of the Center yet reaps the full benefit of all Center activities, a research program that could easily cost more than $10 million per year to operate in an industry or government facility.
More information on CHREC can be found at www.chrec.ufl.edu.
Dr. Alan D. George is Professor of Electrical and Computer Engineering at the University of Florida, the flagship university in the fourth largest state in the US, where he serves as Director of the HCS Research Laboratory, Chair of the University Committee on High-Performance Computing, and Director of the new NSF Center for High-Performance Reconfigurable Computing. He received the B.S. degree in Computer Science and the M.S. in Electrical and Computer Engineering from the University of Central Florida, and the Ph.D. in Computer Science from the Florida State University. Dr. George's research interests focus on high-performance architectures, networks, services, systems, and applications for reconfigurable, parallel, distributed, and fault-tolerant computing. He is a senior member of IEEE and SCS, a member of ACM and AIAA, and can be reached by e-mail at firstname.lastname@example.org.