HyperTransport Gets One Last Speed Bump Before QuickPath Deploys
On Monday the seven-year old HyperTransport (HT) Consortium announced it was boosting the maximum bandwidth of its HT interconnect and associated HTX connector. The new specifications are aimed to keep pace with the next generation of high performance, low latency platforms based on HyperTransport links. Since AMD introduced the technology in 2001, HyperTransport has been the leader in chip-level and board-level interconnect performance, especially in the HPC space.
The new HyperTransport 3.1 specification will support a top speed of 3.2 GHz, which translates into 6.4 gigatransfers/second (23 percent more bandwidth than HT 3.0). At the maximum 32-bit link width, that works out to 51.2 GB/second. But according to Mario Cavalli, general manager of the HyperTransport Technology Consortium, since 16-bit links still provide considerable performance with a much less challenging design, vendors haven’t yet ventured into the 32-bit realm. Thus the practical bandwidth limit is more like 25.6 GB/second. “I think it’s safe to say that so far, 32 bits is still considered to be a challenge from a design point of view,” he explained.
Coincidentally — or maybe not — 25.6 GB/second is thought to be the maximum bandwidth of Intel’s first implementation of their new QuickPath interconnect, which is making its debut in the chipmaker’s upcoming Nehalem processor line. Since this week’s Intel Developer Forum (IDF) is the coming out party for Nehalem, Intel may provide some more specifics about the QuickPath performance. Intel’s new interconnect is expected to give its new microprocessors parity against AMD’s HT-powered chips. The first Nehalem products are expected to be available before the end of the year.
Certainly AMD — the main driver of HyperTransport technology — would like to maintain the pole position in chip-level and board-level interconnect technology. Since AMD introduced HyperTransport in 2001, it has used the technology as a major differentiator against Intel designs that relied on the slower and latency-challenged front-side bus (for on-chip communication) and PCI bus (for off-chip communication). Whether the HT Consortium announcement on Monday was timed to blunt any QuickPath news at this week’s IDF event is conjecture.
The consortium’s position is that the 3.1 release is just another planned speed bump on their technology roadmap to keep ahead of vendor deployments. “With HyperTransport 3.0 we have 2.0 GHz implementations shipping today,” notedJeff Underhill, chair of ecosystems, for the HT Consortium and business development manager for AMD. “If you look at the maximum bandwidth of a 16-bit 2.0 GHz link, that means we have 4.8 GB/second of headroom today. This may provide enough for the immediate future, but as we look at the horizon, we see increasing core counts, I/O bandwidth and memory bandwidth, so we really need some additional headroom to pave the way.”
As far as the new connector spec goes, HTX3 triples the performance of the original HTX 1.0 design, while maintaining backward compatibility. At 5.2 GT/second (20.8 GB/second on a 16-bit link), the technology should match pretty well with the maximum bandwidth supported by the HT 3.1 spec. HTX3 also adds power management, in which link width and frequency can be adjusted to optimize energy use. Connected devices will also be able to participate in on-board power optimization, for example sleep state transitions. The idea is to fit within the same power envelope of a PCI Express link.
This is actually an important characteristic, since HTX connectors are able to use the physical PCI connector on a motherboard to get access to the CPU. However unlike PCI, HTX offers a direct, low-latency pipeline to the CPU. This makes HTX a good solution for custom co-processor acceleration, especially FPGAs. The consortium is hoping that if the market expands enough, motherboard manufacturers will be willing to incorporate native HTX slots on their boards.
As it stands today, the HT Consortium is positioning HTX as the high performance solution for off-chip communications, yielding the general-purpose role to PCI. Whether this differentiation holds depends on the technology path of PCI. Intel is lobbying for its Geneseo technology to fulfill the HTX role in the upcoming PCIe 3.0 standard, but it remains to be seen if the PCI SIG will take this on. If Geneseo falls by the wayside, Intel may end up inventing a QuickPath connector with the equivalent functionality. For now, the co-processor solution for Intel is its QuickAssist technology on top of the existing front-side bus.
The biggest roadblock for HyperTransport is its inability to penetrate into Intel platforms. As such, the success of HT is tied to the success of AMD in the market. Fortunately, applications for high performance interconnects are not just in the traditional HPC space anymore. AMD has lost market share there in the past couple of years, so HPC growth opportunities are more uncertain now. But like a lot of HPC technologies, HyperTransport may be able to extend into other areas as the demand for high bandwidth, low latency performance becomes more generalized. The broader enterprise space (severs and routers), workstations, and even PC gaming are emerging opportunities, according to Cavalli. He believes the commoditization of high performance communication is going to be very important for HyperTransport down the road.
“We are already working on the future as we speak,” said Cavalli. “At the end of the day, we will continue to carry the torch for high performance opportunities, especially on the low latency side and for super high bandwidth applications.”