With all the recent hoopla about GPU-accelerated HPC, reconfigurable computing with Field Programmable Gate Array (FPGA) has been getting proportionally less attention. While NVIDIA has led the GPU push in HPC, there is no single vendor in the reconfigurable computing space that has jumped into the driver’s seat. That hasn’t kept a variety of smaller players from trying.

Unlike GPUs — or CPUs for that matter — FPGAs require an unconventional programming model. This stems from the fact that the chip’s logic elements must be custom-configured before applications can run on them. This process is accomplished via software, which in this case is used to implement the best-fit hardware design for the application code. This is not something the average programmer is trained to do. Some have likened it to writing assembly code, but it is actually worse that. It’s more like designing the assembly language itself.

The attractiveness of FPGAs is that they can be custom configured to run specific application workloads efficiently. If a different workload needs to be run, the FPGA can be reconfigured accordingly. Switching configurations takes just milliseconds.

Like GPUs, FPGAs can offer as much as one or two orders of magnitude performance gain for certain applications and can do it with a fraction of the power consumption of a CPU-only implementation. While a perception exists that there is a battle between FPGAs and GPUs for general-purpose HPC acceleration, there’s actually plenty of daylight between the two architectures that suggests different classes of applications would gravitate toward one or the other. For example, most bioinformatics applications, which are integer based and highly parallel in nature, are ideally suited to FPGA silicon, but would not be particularly applicable to GPUs. Image recognition (but not rendering), encryption/decryption, and FFT-based codes are also good fits for FPGAs.

The fact that FPGAs are standard gear in high performance appliances like market data feeds, network routers, military systems, and medical imaging devices points to their applicability for streaming HPC workloads. But since FPGAs are mainly intended for embedded platforms to replace or augment digital signal processors (DSPs) or other custom ASICs, their entry into the world of servers and workstations, where the majority of HPC is performed, has been relatively recent. Fortunately developments in the reconfigurable computing arena have been coalescing over the past couple of years to make life more hospitable for FPGA-based HPC acceleration.

Since 2006, the opening up of AMD’s HyperTransport interface, via Torrenza, and the subsequent licensing of Intel’s Front Side Bus (FSB) has made FPGA coprocessing a much more practical endeavor. Companies like XtremeData, DRC Computer, and Nallatech have picked up on this and developed FPGA expansion modules for x86-based platforms. Prior to this, only custom solutions such as SGI’s RASC (Reconfigurable Application Specific Computing) technology and Cray’s XD1 system were possible.  This relegated reconfigurable computing to research projects and government buyers with deep pockets. The ability to hook an FPGA onto an x86 system bus dramatically expands the market.

Making FPGAs socket friendly also gives the devices an interesting advantage over GPUs. While NVIDIA’s Tesla and AMD’s FireStream devices communicate to the host via a PCIe link, socketed FPGAs can talk to the CPU directly, using the native processor bus. This provides latencies on the order of 250 ns — less than half what can be achieved over PCIe. Being on the bus also means an FPGA has peer access to the processor’s memory and can operate without host intervention.

With FPGAs playing nice with x86 hardware, reconfigurable computing toolmakers such as Mitrionics, Celoxica, and Impulse Accelerated Technologies have been hooking up with the FPGA board makers and OEMs (like HP) to offer more integrated acceleration solutions. The toolmakers offer programming environments that allow developers to write C (or C-like) code that can be compiled into an FPGA logic design, which can subsequently be loaded onto the chip. Although this alleviates the developers from the more difficult task of doing low-level hardware design via VHDL or Verilog, even at this level the programming of FPGAs remains the most tenuous step in reconfigurable computing.

The fundamental problem is that the tools offered do not entirely shield the programmer from hardware design issues, nor do they use a standard programming environment. In the case of Celoxica, Handel C is used as a hardware design language to define the FPGA implementation. Similarly, Mitrionics invented Mitrion C, which employs the Mitrion Virtual Processor as an intermediate representation of the final hardware design. In both cases, these languages are not standard C in any sense, so they rely upon custom compiler, runtime and debugger technologies and force the customer to maintain vendor-specific source code.

Impulse Accelerated Technologies created Impulse C, which is compatible with standard C, but extends the language’s capability with some extra data types and library functions for FPGA computing. This has the advantage of allowing the developer to maintain a C source base and use standard debugging tools for development. Once debugging is complete, the Impulse compiler is used to generate the FPGA bitmap image corresponding to the C code intended for acceleration. Impulse C is designed for streaming applications, but can be adapted for a shared memory model as well.

The most integrated and most ambitious reconfigurable computing solution today is the recently announced Convey Computer “hybrid core” platform, which wraps multiple Xilinx FPGAs into a reconfigurable coprocessor alongside an x86 CPU. The use of application workload “personalities” (essentially pre-canned FPGA bitmaps) shields the developer from hardware design issues or even explicit parallel programming, leaving the compiler and runtime system to sort out the CPU and FPGA code mappings. The entire system can be programmed with ANSI standard C/C++ and Fortran, eliminating one of the largest barriers to programmer productivity for accelerator-based architectures.

Because of its compatibility with standard programming languages, the Convey offering has the potential to make coprocessor acceleration — FPGA-based or otherwise — a lot more accessible to HPC users. That doesn’t necessarily mean other reconfigurable computing solutions will be left behind. There should be room in the market for FPGA expansion modules that can be applied across a range of server platforms, and the first generation of reconfigurable computing toolmakers can develop software components for a growing ecosystem.

In fact, David Pellerin, co-founder and CEO of Impulse Accelerated Technologies doesn’t consider Convey a competitor. Rather, he believes the C and Fortran workflow is a good model to foster for FPGAs and thinks the Impulse offerings could have a place in such an environment. “I believe our tools could play a role in allowing Convey ‘personality’ developers — such as system integrators and algorithm domain specialists — to more quickly create these FPGA-based library elements,” says Pellerin.

While there’s little reason to expect a huge rush of HPC applications to FPGA-based systems, steady progress in reconfigurable hardware and software should enliven the market over the next couple of years (software standards certainly wouldn’t hurt either). As the latest 65nm FPGA silicon devices — Xilinx Virtex-5 and Altera Stratix III — starts to make their way into HPC platforms, more silicon real estate will be available for even larger problems, especially ones involving a lot of floating point parallelism. With the advent of HyperTransport 3.0 and Intel’s QuickPath interconnect bus for the Nehalem processor family, higher performing x86 coprocessor links will soon be available. And finally, as the introduction of the Convey architecture demonstrates, reconfigurable computing can be completely encapsulated, offering the power of FPGAs with a friendly face.