July 13, 2009

Beyond Speeds and Feeds

By Geoffrey James

How chip architecture is redefining high-performance computing productivity.

High Performance Computing (HPC) was once limited to a select group of laboratories where scientists or engineers solved complex problems on huge mainframe “supercomputers” that cost millions of dollars to buy and maintain. Today the drop in the price of computer power has combined with new architectures for clustering to bring HPC to a wide range of applications inside a growing number of industries at a reasonable price.

“Computer power is the raw fuel for business innovation,” explains Dr. Jeff Layton, enterprise technologist for HPC at Dell Inc. “Making HPC available to a wider range of customers, and making it more cost-effective, will have a long-term effect, not just on productivity but also on the ability of companies to thrive, not only during difficult economic times but also for many years to come.”

Along with this democratization of HPC has come a growing understanding, among pundits and executives alike, that the traditional way of measuring HPC—the raw performance of a single CPU—seems out of date. As the computer industry leaps to more-complex computing environments, it has become clear that HPC performance must be redefined in order to encapsulate the wider business case, according to Scot Schultz, AMD’s senior strategic alliance manager for HPC.

“What’s important is not how fast the CPU can run a test suite but how effectively it can solve a real-life problem,” Schultz says.

Productivity Now Trumps Raw Performance
More and more analysts, OEMs and IT executives have come to understand that raw performance is less important than how the underlying architecture makes end users more productive. “The performance that’s actually delivered to end users is highly dependent on the chip architecture and how well the software can take advantage of it,” explains Layton.

IT managers who make HPC buying decisions based purely on those obsolete measurements risk getting less bang for their buck, according to John Spooner, an analyst at the market research firm Technology Business Research (TBR). “There are always going to be customers who want all-out performance and don’t care about anything else,” he admits, “but many companies are now embracing the idea that the greatest business value comes not from raw performance but from getting the maximum performance for your overall IT dollar.”

Companies that adopt HPC are typically less interested in “speed and feeds” than in creating a long-term competitive advantage. A case in point is the sport department of Ferrari, one of the first companies to test Microsoft’s Windows HPC Server 2008.

“Ferrari is always looking for the most-advanced technological solutions, and the same goes for software and engineering,” says Piergiorgio Grossi, head of information systems at Ferrari. Like many other companies embracing HPC today, Ferrari is using it widely across the corporation—“for our users, engineers and administrators,” Grossi says.

Companies need to be thinking about productivity as a performance measurement, according to Vince Mendillo, director of marketing for the HPC business group at Microsoft. “HPC is expanding into vertical markets, ranging from engineering to aerospace to energy and many other industries,” he explains. “Ultimately, HPC is about helping customers get the job done.”

Measuring Productivity
HPC has traditionally been measured in terms of the raw computing power of a single core on a single CPU. Using that primitive metric, the battle for “market leadership” has been primarily between the two leading CPU firms: AMD and Intel, according to Rob Enderle of the Enderle Group. “For decades, these two companies have traded positions as the ‘industry leader’ when it comes to raw performance figures,” he says.

It’s a contest that’s likely to continue for the foreseeable future, according to Ken Cayton, research manager for enterprise platforms at the market research firm IDC. “Both companies are constantly moving forward, so one would expect to see the same kind of leapfrog behavior we’ve seen so frequently in the past,” he says.

However, IT executives need to be aware that the traditional “speeds and feeds” measurement is largely irrelevant in a world in which HPC takes place on CPU chips that contain multiple cores, which are, in turn, harnessed into clusters. In a multiprocessing environment, other metrics such as power efficiency start becoming more important, according to TBR’s Spooner. “Because energy costs are such a big proportion of the expense of running a large data center, businesses now want to maximize the amount of work they get done for each unit of electricity they pay for,” he explains.

Indeed, some companies are finding that the hard limitation of their HPC computing isn’t raw performance but the amount of electricity they can get piped into their data center. Cayton relates an experience he recently had with a Manhattan firm that is doing financial analysis but has only a limited amount of power coming into the building. “It therefore is more concerned with how effectively its HPC system uses power than it is about how quickly one element of the system can perform calculations,” Cayton explains.

Architecture and Performance
With multiprocessing and clustering, the speed of an individual core is often far less important than the ability to move data around between the various chips, explains Jordan Selburn, principal analyst at the market research firm iSuppli.

“In a lot of areas and applications, raw horsepower isn’t a significant factor, because other standards drive the degree of speed needed and anything excess is just that: excess,” Selburn explains. “The key in HPC applications is how efficiently you can perform the needed function.”

And that efficiency is intimately tied to the underlying architecture of the CPU chip, according to Einar Rustad, vice president of business development at Numascale, a company that makes chip sets that link multiple CPUs into HPC clusters. “The challenge with multiprocessing is keeping everything in sync, which means that each CPU must have swift access to the data that’s been processed by the other CPUs,” he explains.

To accomplish this, the cluster must be able to move data around quickly, something the HyperTransport™ architecture that AMD uses makes relatively easy. “With other chip architectures, you have to move data around by using the front-side bus, which is not only ungainly from an electronics viewpoint but also incurs a lot of overhead and prevents a true shared memory architecture with cache coherence,” says Rustad. “AMD’s HyperTransport technology, by contrast, makes it easier to connect CPUs together in a way that enables programmers to address the combined memory space and to benefit from the aggregated memory bandwidth.”

One benefit of directly connecting the chips is a potential decrease in data latency, which means that each CPU in the cluster will spend less time idling and more time actually processing data, according to Gilad Shainer, director of technical marketing for Mellanox Technologies, a leading supplier of semiconductor-based server and storage interconnect products.

“AMD has a good vision of how HPC should be handled,” Shainer says. “Its technological architecture provides value for many applications and end users, which is why we’re happy to collaborate with it to build the kind of balanced systems that companies want to buy.”

Real-Life Productivity
A chip architecture that handles data more efficiently can also make life easier for HPC programmers—an important issue in IT groups that may have limited access to top programming talent.

“One of the big limitations in HPC is adapting programs to run in parallel,” says Dell’s Layton. “The computer industry has been struggling for years with limitations on memory bandwidth per core, but that’s finally beginning to ease up, largely as the result of improvements in basic CPU architecture.”

Because programming for HPC is becoming easier, it’s beginning to show up in more industries and application areas. And that, in turn, has further lessened the importance of raw computing power as the primary HPC benchmark, because every industry has different requirements when it comes to the type of computing power that’s applicable to that industry. For example, financial HPC applications make extensive use of floating point, an area in which AMD’s architecture has a “slight edge” over other architectures, according to Christian Heidarson, an analyst at the market research firm Gartner.

HPC-friendly chip architecture can also make a future upgrade path easier. “Because HPC applications tend to be complex, companies are leery of pulling out their current systems and replacing them with new ones,” explains Layton, who notes that AMD has been designing CPU architectures that are socket-compatible, making it possible to upgrade a system without reloading and reconfiguring the software. The only change to the system that’s required is a BIOS upgrade, which takes a few minutes as opposed to the hours or days it might take to completely reconstruct a clustered system. “This makes it possible for a company to upgrade while limiting the downtime and cost risks inherent in re-creating and reinitializing the entire cluster,” says Layton.

In short, the raw performance of a single CPU may not be the best measurement of HPC. Rather, a metric such as the total cost of ownership (TCO) can provide a better baseline by which to judge systems and their underlying chip architecture.

“It’s a big change from the way people are used to thinking about HPC,” says AMD’s Schultz. “However, focusing on productivity means that companies can purchase their computer power more wisely and get the most benefit from their IT dollars.

For more on HPC solutions based on AMD Opteron™ processors go to www.amd.com/istanbulsolutions.

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