Here is a collection of highlights from this week’s news stream as reported by HPCwire.

GE Uses GPGPU Technology in Rugged Platforms

PRACE Grants 4.3 Million Core Hours to Prototype Systems

AMD Announces Strong Infrastructure for Upcoming ‘Magny-Cours’ Line

Eurotech Launches Aurora Au-5600

Clustercorp Releases Rocks+ 5.3

QLogic Announces Expanded Product Suite from EMC Select

Intel Launches Xeon Processor 5600 Series

Cray’s CX1 Deskside Supercomputers Now Available with Intel Xeon 5600 Series

KAUST Hits The Ground Running with Totalview

R Systems Selects ScaleMP for Dynamic Virtual SMP Provisioning

Supermicro Servers Support Intel Xeon Processor 5600/3600 Series

New BOXX Rendering System Features Six Core Processors and Solid State Drives

SGI Announces Support for Intel Xeon Processor 5600 Series

Cycle Computing Launches CycleCloud for Life Sciences

CLC bio Releases Whole-Genome de novo Assembler

India Throws Hat Into Petaflop Race

Ever since Roadrunner broke the petaflop barrier in June of 2008, other organizations have been eager to follow suit. One of the latest groups to make its plans known is Pune, India’s Centre for Development of Advanced Computing, or C-DAC.

In a recent Financial Chronicle article, author Michael Gonsalves reports that C-DAC intends to create a brand-new PARAM supercomputer, a lean-green petaflop computing machine. The Director of C-DAC, SP Dixit, relayed plans to provide supercomputing technology at a cheaper rate in order to compete with the American market.

The total cost of the project will be almost $220 million (Rs 1,000 crore) and the daily maintenance costs alone will run around $50,000 (Rs 20-25 lakh) per day, according to Rajan T Joseph, director general for C-DAC. Wow, $50,000 per day comes out to $18 million per year. At first I thought it might be a mistake, but after doing some sleuthing, I found out that energy bills at supercomputing centers commonly run into tens of millions of dollars a year.

So it makes sense CDAC officials there state that the biggest obstacle will be related to powering the system. Their current teraflop system, PARAM Yuva, requires 1 MW of power, but a petaflop system will use 20 MW, which will necessitate a separate power station. Still, they hope to have the system completed by 2012.

PARAM Yuva is being used for applications such as computational electromagnetic simulation. Already the machine has done computations consisting of two billion cell points, and will next be attempting a simulation with four billion cell points, which will set a world record, said Hemant Darbari, executive director of C-DAC.

So far, the only two publicly-announced petaflop systems are in the US — Jaguar at Oak Ridge National Lab and Roadrunner at Los Alamos National Lab – but over the past few months, petaflop projects have been announced in China, Japan and most-recently in Russia, in addition to other US petaflop projects that are underway, like Blue Waters.

IBM Researchers Have No Place to Go But Up

When you have a small living space, IKEA urges you to go vertical. Well, in a similar fashion, a partnership of IBM and Swiss researchers are considering vertical integration techniques to be able to fit more transistors on a chip and in the process keep Moore’s Law alive for another 15 years.

Moore’s law states that the number of transistors that can be placed on a chip will double every 18 months. It’s been in effect for over 50 years, but the chips are running out of horizontal space, so there’s no place to go but up. This technology is called 3D integration.

From the article:

Last week, IBM, École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH) signed a four-year collaborative project called CMOSAIC to understand how the latest chip cooling techniques can support a 3D chip architecture. Unlike current processors, the CMOSAIC project considers a 3D stack-architecture of multiple cores with a interconnect density from 100 to 10,000 connections per millimeter square. Researchers believe that these tiny connections and the use of hair-thin, liquid cooling microchannels measuring only 50 microns in diameter between the active chips are the missing links to achieving high-performance computing with future 3D chip stacks.

“In the United States, datacenters already consume two percent of the electricity available with consumption doubling every five years. In theory, at this rate, a supercomputer in the year 2050 will require the entire production of the United States’ energy grid,” said Prof. John R. Thome, professor of heat and mass transfer at EPFL and CMOSAIC project coordinator. 3D chip stacks with interlayer cooling not only yield higher-performance, but more importantly, allow systems with a much higher efficiency, thereby avoiding the situation where supercomputers consume too much energy to be affordable.

There have been challenges along the way. Designing the system on a chip (SoC) in multiple tiers reduces the average distance between system components, which improves efficiency and performance, but also generates more heat. So the researchers must use advanced cooling techniques in conjunction with the 3D architecture. Well, as it turns out, IBM and ETH had previously developed a novel water-cooling technology for the Aquasar supercomputer. The heat removal system uses liquid-filled microchannels that work like sponges, absorbing the heat and drawing it away. The researchers are hopeful that the technique will lead to practical 3D systems.