Sometimes Accomplishment Is Starting Something New Rather than Finishing Something Old
So perhaps it was of this last year of the first decade of the first century of the new millennium in the field of high performance computing. Not to minimize the continued progression of petaflops computing as we enter Year 3 AP (After Petaflops). With the addition of new machines both deployed and planned, petaflops-scale applications, as acknowledged by the Gordon Bell Prize, steady increase in the number of cores per socket, and the uncomfortable marriage of GPUs in heterogeneous structures — the last year has been marked by continued and demonstrable advances. As petaflops computing has become truly international in scope and application, this emerging system class is no longer an ethereal fringe, but rather has gained firm traction at such power houses (yes, meant in more than one way) as Oak Ridge National Laboratory, where they now serve humanity as the heavy lifters in computational methods addressing the challenges of the modern world.
But one potentially important accomplishment in the last twelve months is not something that has been completed; instead, it is something that has been just initiated. Even as we gain a footing in the era of petaflops computing, we have set in motion the exploration of the undiscovered domain of exaflops computing. This year has seen the launching of multiple programs to develop the concepts, architectures, software stack, programming models, and new families of parallel algorithms necessary to enable the practical realization of exaflops capability prior to the end of this decade. These have involved unprecedented cooperation and coordination within government agencies and laboratories, industry, academia, and internationally. At the dawn of the petaflops era, the emerging focus on the performance regime three orders of magnitude beyond is unlike anything before it and in stark contrast to the grass-roots workshops towards petaflops back in the relaxed days of the run-up to teraflops in the 1990s.
There are good reasons for this. The challenges facing the continued delivered sustained performance across a broad range of application domains are dramatic and reflect a corner turning on the trends that have driven us forward, ultimately due to Moore’s Law and the semiconductor revolution. These, somewhat over simplistically, can be summarized as: concurrency, power, reliability, and productivity.
In the past, the double-whammy of increases in clock rate and increases in processor core complexity delivered two decades of sustained exponential growth in processor core performance which when integrated in clusters of SMP nodes has given us the iconic images of straight lines on semi-log graphs with respect to the passage of time. Now the S-curve is bending for a second time, and not in a good way. Power has hit the threshold of pain, and the architecture tricks have been largely exhausted. Increased resources have been dedicated to confronting the egregious impact of the memory wall and the latencies and blocking incurred. Ever decreasing efficiencies (single digit not uncommon) by several normalization factors (e.g., FLOPS, utilization, per transistor, per joule, per hectare) have exposed the soft underbelly of an ultimately unsustainable golden age: exponentials cannot go on forever.
Indeed, the authors have projected that “we will never achieve sustained zettaflops computing” using the hardware paradigm of Boolean logic gates and binary data storage. Due to the speed of light, Boltzmann’s Constant, and atomic granularity it is predicted that the wall, which is more like a very steep hill will occur at about 32 exaflops. But we are not there yet; indeed, there are a good four orders of magnitude to go. And that will be hard.
Three major activities can be cited that have just been created during the last year to engage the talents of the international community including experts in: hardware, software, algorithms, and domain science. These have resulted from at least two years of preliminary workshops and studies sponsored by diverse entities and internal industry planning as well. These are: IESP, DOE X-Stack, and DARPA UHPC. There are many smaller activities as well.
The International Exascale Software Project (IESP) has brought together the interests, talents, and resources of the international community to cooperate and coordinate long-term development of the necessary software infrastructure required to enable effective exaflops-scale performance before the end of this decade. Learning from past experiences where software always appeared to lag behind the hardware, this world-straddling endeavor is driven by the recognition that to succeed, the software needs to be there when the hardware is. More importantly, the hardware designs must be informed by the needs of the software so that there is minimum mismatch and the concomitant ensuing generations of unsatisfactory patches. But there is an even more critical imperative: the realization that without the right software, exaflops may not be achievable at all (except in special cases) and that no one nation can go it alone; the HPC community is just too small for multiple conflicting paths of a top to bottom software refactoring. In the last year, four multi-day meetings in France, Japan, and the UK among representatives of all of the major HPC nations have provided an emerging roadmap to inform future planning of the joint development of the full supporting software infrastructure for Exascale systems’ operation and programming.
The US DOE has also begun a new program of research with the release of its recent RFP to develop the components of the “X-Stack,” the software required to enable a new generation of science and technology applications with the advent of future exaflops capable systems. These elements include operating systems, runtime systems, programming models and tools, and methods for reliability and mass storage and I/O. The winners, not yet announced, will represent a new wave of research in the US combining partners in the national laboratories, industry, and academia driven by the requirements of major mission-critical applications. This and other related DOE programs were developed in part from an extensive series of community workshops through the preceding year on application domains, hardware and software systems, and mathematical algorithms. This research will join other programs around the world in the first concerted effort to turn the corner and set a new trajectory for future HPC system software architecture, design, and implementation.
Perhaps most dramatic and at the same time risky undertaking is the new DARPA Ubiquitous High Performance Computing (UHPC) research program. UHPC is intended to attack the above challenges through nothing less than revolutionizing HPC system design. Through a lengthy program development process that involved three separate studies in technology, software, and resiliency engaging the talents of experts throughout the US, UHPC evolved an energetic research charter to reinvent computing prior to the end of this decade. The program was not explicitly targeted to exascale but rather to the mid-range of one or some unspecified number of interconnected and interoperable racks, each capable of approximately 1 petaflops sustained performance with a power budget of less than 60 kilowatts.
At the foundation of this program is the call for a new model of parallel computation to replace the venerable and highly successful message-passing model that has dominated for the last two decades. A major emphasis is on power reduction with an average energy of 25 Pico-Joules per floating point operation. A thousand such racks if sufficiently efficient would deliver 1 exaflops for 20 megawatts.
Emphasis is placed on the co-design of both hardware and software components in response to challenge problems that will span the applications domains from some of the largest STEM problems to heavy real time I/O streaming to knowledge management graph problems. Scaling down is as important as scaling up to UHPC, with single modules capable of multiple teraflops (and in mobile modules this is an important operating point).
The program may run eight or nine years and result in one or more prototypes of fully-operational systems. The first half of the program, Phases 1 and 2 spanning four years, will begin this summer with the winning teams to be announced in a month’s time. Atypical of such programs is the expectation of strong cooperation among competing teams and the delivery of much of the techniques and technology to the research community throughout the four phases of the program.
This year has indeed been a very productive year, both for its accomplishments in the deployment and application of petaflops-scale systems and for its forward-looking inauguration of the exaflops era.