Here is a collection of highlights from this week’s news stream as reported by HPCwire.

NIST Awards $50M in Grants for the Construction of Five Science Facilities

National Center Presents Strategy to Revitalize US Manufacturing

NSF Funds Computer Systems Research Center at New Mexico Consortium

Pervasive Software Announces Multicore-Ready Pervasive PSQL v11 MC

Mellanox Adapters Support Dell Blade Servers

Three Tiny Qubits, Another Big Step Toward Quantum Computing

Louisiana Optical Network Used to Study Hurricane Effects on Spilled Oil

Study Shows Financial Firms Short On Resources for Analytics Needs

Computer Simulation Aimed at Green Building Design

HP Completes Tender Offer for and Merger of 3PAR

Massively Parallel Technologies Unveils “Blue Cheetah” Software Model

LANL Buys Two SGI Altix XE Clusters

IBM to Acquire BLADE Network Technologies

Pervasive DataRush on SGI Altix Shatters Smith-Waterman Throughput Record by 43 Percent

Sophis Announces Partnership with Platform Computing

Intilop Announces Record Breaking Latency for 10Gb TCP Offload Engine

Fujitsu Starts Building 10 Petaflop Japanese Super

In the Japan/US race for supercomputing prowess, Japan just pulled ahead when Fujitsu announced it had started shipping parts for the next-generation, 10-petaflop “K” supercomputer, to be housed at the RIKEN lab in Kobe, Japan.

The name for the system — “K” — comes from the Japanese word “Kei” for 10^16, the numerical representation for 10 petaflops. The character for “Kei” also connotes a large gateway, symbolizing the system’s potential to be a gateway for scientific process and the benefits it bestows on Japanese society.

The Next Generation Supercomputer project is being jointly developed by the RIKEN research institute and Japan’s Ministry of Education, Culture, Sports, Science and Technology (MEXT). MEXT’s stated goal for the project? To develop and build the world’s most advanced and powerful next-generation supercomputer. But said supercomputer is not expected to be fully operational until autumn 2012.

If “K” achieves its 10 petaflop goal by 2012, it could take the coveted top position on the TOP500 list, but two years is a long time in the multi-petaflop race, enough time perhaps for one of the current top spot holders (or a new contender) to lay claim to the “world’s best” designation.

When the supercomputer reaches completion, its advanced architecture will consist of more than 800 computer racks containing 80,000 SPARC 64 VIIIfx processors connected by an innovative six-dimensional mesh-torus topology — both the chips and the interconnect were developed by Fujitsu. Each processor sports 128 gigaflops, running at just 2.2 gigaflops per watt — power consumption levels that are two-thirds less than the chips’ predecessors. The system will use water-cooling to enable high-mount densities, extend component life and and reduce failure rates.

It’s interesting to note that “K” may be one of the last big homogeneous (CPU-only) big machines we will see, given the current trend toward heterogeneous computing, using specialized processors, such as GPUs, to achieve speedups beyond the capability of single architecture systems. Prior to the Great Recession, Japan’s Next-Generation Supercomputer was going to employ vector units in addition to the standard scalar CPUs, but those plans were crushed under the wheels of a tanking economy. Final analysis: 10 petaflops is a pretty serious goal for a single-architecture scalar system, hence the need for so many processors (80,000) — a requirement that brings up a host of other challenges, for example, paying for all of them. A Register article does the math:

At a $4,000 a-piece volume street price (what a high-end Itanium or Xeon processor sells for), that would be $320m just for the processors. It is likely that the chips, even at these volumes, cost more than this.

The Reg piece also does a good job reminding us how economic forces almost put the kibosh on the project.

And the awards go to…

It’s that time of year again when a trifecta of big-time awards are announced. The Ken Kennedy Award, the Sidney Fernbach Award, and the Seymour Cray Award recipients have been selected. The awards will be formally presented at SC10 in New Orleans on November 17.

The second annual ACM-IEEE Computer Society Ken Kennedy Award honors Intel Fellow David Kuck for his contributions to compiler technology and parallel computing that have improved the cost-effectiveness of multiprocessor computing. Established in 2009 in honor of the late Ken Kennedy, the award recognizes substantial contributions to programmability and productivity in computing as well as significant community service or mentoring contributions, and carries a $5,000 honorarium. Kuck was also the recipient of the IEEE Piore Award and the 1993 ACM-IEEE Computer Society Eckert-Mauchly Award.

From the announcement:

Kuck’s pioneering techniques are incorporated in every optimizing compiler in use today. His impact spans four decades and embraces a broad range of areas, including architecture design and evaluation, compiler technology, programming languages, and algorithms. During his career, he influenced the design of the Illiac IV, Burroughs BSP, Alliant FX, and Cedar parallel computers. The Kennedy Award also cited him for the widespread inspiration of his teaching and mentoring.

UC Berkeley Professor James Demmel receives the 2010 IEEE Computer Society Sidney Fernbach Award for advances made to high-performance linear algebra software. In memory of high-performance computing pioneer Sidney Fernbach, the award was established in 1992 to recognize outstanding contributions in the application of high-performance computers using innovative approaches. The award consists of a certificate and a $2,000 honorarium.

From the release:

The software and standards Demmel developed enable users to transition their computer programs to new high-performance computers without having to re-implement the basic building blocks. The software is used by hundreds of sites worldwide, including all U.S. Department of Energy national laboratories, NASA research laboratories, many universities, and companies in the aerospace, automotive, chemical, computer, environmental, medical, oil, and pharmaceutical industries.

Last up, the IEEE Computer Society’s prestigious 2010 Seymour Cray Computer Engineering Award goes to IBM’s Dr. Alan Gara for innovations in low power, densely-packaged supercomputing systems. There is no official announcement out yet for the Cray Award, but the winner is listed on the award website. The Seymour Cray Award was established in late 1997 to recognize innovative contributions to high performance computing systems that best exemplify the creative spirit demonstrated by the late Seymour Cray. Honorees are presented with a crystal memento, illuminated certificate, and $10,000 honorarium.

This is not the first time Dr. Gara, chief architect of the BlueGene supercomputer, has been honored for his influential achievements. Gara received the Gordon Bell Prize in 1998 for the QCDOC machine, a custom supercomputer optimized for Quantum Chromodynamics, and he was part of the team that won a 2006 Gordon Bell Prize for Special Achievement for work on The BlueGene/L Supercomputer and Quantum Chromodynamics.

Congratulations to all the recipients!