Although Egypt is not exactly the epicenter of high-end computing, a tech startup based in Cairo is looking to make its name in an emerging area of HPC. SilMinds has developed hardware accelerator technology designed to speed up a growing set of financial computing applications. The resulting products represent one of the few hardware-based solutions that support decimal floating point (DFP) math.

SilMinds was founded in 2007 as a research, design and consultancy firm, which is initially focused on providing industry standard IP cores for decimal floating point applications. The company’s chief technology officer, Professor Hossam A.H. Fahmy, was a member of the committee that formulated the IEEE 754-2008 standard for floating point arithmetic, including DFP. According to the SilMinds website, the first products were developed with grant money from the EU-Egypt Innovation Fund.

The company’s initial offering, SilAx, is a configurable vector DFP coprocessor implemented with FPGAs. The card can be equipped with either Altera or Xilinx FPGAs and hooked into any standard PCIe slot with at least four lanes. That makes it compatible with a wide array of x86 servers, HPC or otherwise.

No commercial deployments are yet claimed though. The company is currently talking with solution providers that deal directly with telecom and bank institutions, presumably with the idea of wrapping a complete solution around the SilMinds accelerator and offering it as a turnkey platform.

Keep in mind that decimal floating point operations are a bit of an outlier when it comes to computing. Most applications are performed using binary arithmetic, the natural style of number crunching for microprocessors. Decimal arithmetic can be performed with fixed-point (non-floating point) calculations, but the representations are too limited to support industrial strength money operations.

For example, adding $0.10 to $1.99 is fairly straightforward using fixed-point notation. But even doing something as simple as computing a 10 percent sales tax is problematic, given that 1/10 can only yield an approximate value when converted to binary. Where money is concerned, that’s not a good thing. Round-off errors add up and on a large scale can mean thousands or even millions of dollars end up in the bit bucket.

Decimal floating point, on the other hand, is able to support a much wider range of values than is available for fixed point, and provides much greater precision. Up until fairly recently, there was no encoding standard for DFP. But with the release of the IEEE 754-2008, there is now a vendor-independent specification for 32-, 64- and 128-bit decimal floating point representations and their behavior.

Give the regulatory laws imposed upon financial operations these days, DFP is the standard for nearly all applications in banking, telephone billing, tax calculation, currency conversion, insurance, and risk management. Now with the growing streams of real-time financial transactions zipping around the globe, performance and power efficiency have become looming issues. Some estimate that as much as one-third of the world’s server infrastructure is crunching financial data of some sort.

Demand for even more DFP capability appears poised to take off. Mobile networks are becoming ubiquitous across the globe, which should accelerate the need for real-time billing. Cell phones will soon be used as smart credit cards, able to initiate real-time payments at restaurants, movie theaters, and for a variety of other services (This is already in the works in Europe and Asia.). Smart energy grids are also being planned, which will require an extensive infrastructure to compute spot energy pricing. All these applications will require large-scale DFP.

How much demand actually exists for high performance DFP is anyone’s guess. But SilMinds is trying to position itself squarely in the path of this emerging space. So far, competition is minimal. Other than SilMinds, only IBM has decimal floating point implemented in hardware — in this case its z series computers (z9 and z10) as well as its Power6 and Power7 processors. But those solutions are rather expensive compared to a vanilla x86 server equipped with a SilMinds card.

Hardware is the key to performance, as well as power efficiency. Although DFP software libraries exist, they are relatively slow when it comes to compute-intensive DFP applications like large-scale telephone billing. SilMinds has tested its FPGA-based card solution using IBM’s Telco Billing benchmark and reported a 6X speedup compared to a software implementation on a 3 GHz x86 platform. “For other applications we expect that overall speedups will range from 4 to 5x up to 15x” said Assem El Gamal, SilMinds Design Manager. According to him, the variance depends on how much of the application is spent doing decimal floating point computations. In the case of the Telco benchmark, a fair amount of application run time is spent on disk I/O.

When looking at the performance of the DFP calculations in isolation, the results are even more impressive. SilMinds claims an 80X speedup for the core computation, with greater performance possible if the application can benefit from multiple cards.

Using an FPGA-based approach means the solutions can be customized to squeeze the optimal performance from the application. The hardware is implemented in VHDL code, which is designed, written and maintained by SilMinds. Customers tap into the low-level functionality of the accelerator via a set of provided application programming interfaces (APIs); they are not required to write any VHDL code themselves.

Multiple FPGAs per card and multiple card architectures are under study to support multiprocessing and virtualization, with many simultaneous application instances being afforded the maximum speedup needed by each to achieve maximum server resource savings. SilMinds speculates that datacenter TCO and energy saving could be reduced by 80-90 percent. Also under investigation is a network-centric acceleration architecture that could support SaaS and cloud computing.

A DFP ASIC is in the works as well, which according to SilMinds, has already been validated. The idea here is to get the ultimate in performance, sans the reconfigurability of the FPGA. Also on the horizon is a compiler that will generate the appropriate low-level parallel computations without the need for extensive API calls.

With other HPC technology focused on binary floating point capabilities to support scientific applications, the needs of performance-demanding DFP users have largely gone unserved. Financial regulatory requirements, a new floating point standard, and an expanding application space could propel SilMinds and their market into the limelight.