New Architecture Tackles High Speed Network Challenges
Ethernet continues to be the most widely used network architecture today for its low cost and backward compatibility with the existing Ethernet infrastructure. Driven by increasing networking demands for application such as Internet search, Web hosting, video on demand, and high performance computing, network speed is rapidly migrating to 10 Gigabits per second and beyond. But as network speed increases, it poses a number of great challenges on computer servers.
Recently, researchers at University of California, Riverside have studied I/O challenges from high-speed networks and invented a new architecture to efficiently tackle those challenges. A paper describing the research, “A New Server I/O Architecture for High Speed Networks“, was co-authored by graduate student Guangdeng Liao and professor Laxmi Bhuyan. The paper will be presented February 15 at the IEEE International Symposium on High-Performance Computer Architecture (HPCA) in San Antonio, Texas. What follows is an encapsulation of this work and a description of the new I/O design.
Traditional architectural designs of processors, cache hierarchies and system interconnects focus on CPU and/or memory-intensive applications, and are decoupled from I/O considerations. As a result, they tend to be inefficient for network processing. Network processing over 10 Gigabit Ethernet (10GbE) easily saturates two cores of an Intel Xeon quad-core processor. Assuming ideal scalability over multiple cores, network processing over 40GbE and 100GbE will saturate 8 and 20 cores, respectively. In addition to the processing inefficiency, the increasing network speed also poses a big challenge to network interface card (NIC) designs. DMA descriptor fetches over a long latency PCI Express bus heavily stress the DMA engine in NICs and necessitate larger NIC buffers to temporarily keep packets.
These requirements significantly increase the device’s design complexity and price. For instance, the price of a 10GbE NIC can be up to $1,400, while a 1GbE NIC costs less than $40. Therefore having highly efficient network processing with the low complexity of NIC becomes a critical question to answer.
In order to understand network processing efficiency, we used the network benchmark Iperf over 10GbE on Intel Xeon quad-core processor-based servers to measure per-packet processing overhead. It instruments the driver and OS kernel using hardware performance counters provided by the CPU to pinpoint real performance bottlenecks. Unlike existing profiling tools attributing CPU costs such as retired cycles or cache misses to functions, the instrumentation is implemented at the fine-grained level and can pinpoint data incurring the cost.
Through detailed overhead analysis we obtained several new observations, which have not yet been reported.
First, the study found that besides data/packet copy from kernel-to-user space, the driver and socket buffer release unexpectedly take 46 percent of processing time for large I/O sizes and even 54 percent for small I/O sizes. Thus, the major network processing bottlenecks lie in the driver (greater than 26 percent), data copy (up to 34 percent depending on I/O sizes) and buffer release (greater than 20 percent), rather than the TCP/IP protocol itself.
Second, in contrast to the generally-accepted notion that long latency NIC register access results in the driver overhead, our analysis showed that the overhead comes from memory stalls to network buffer data structures. Simply integrating NIC into CPUs like Niagara 2 processors with two integrated 10GbE NICs for reducing register access latency does not help network processing performance a lot.
Third, releasing network buffers in OS results in memory stalls to in-kernel page data structures, contributing to the buffer release overhead.
Finally, besides memory stalls to packets, data copy implemented as a series of load/store instructions, also has significant time on L1 cache misses and instruction execution. Prevailing platform optimizations for data copy, like Direct Cache Access (DCA), are insufficient for addressing the copy issue.
The studies reveal that besides memory stalls, each packet incurs several cache misses on corresponding data and has considerable data copy overhead. Some intuitive solutions like having larger last-level caches or extending the optimization DCA might help network processing performance to some extent, but have major limitations. Increasing cache size is an ineffective approach and more importantly, is unable to address NIC challenges and the data copy issue. Unlike increasing cache size, extending DCA to deliver both packets and those missed data from NICs into caches is more efficient in avoiding memory stalls. The downside is that it stresses NICs more heavily and degrades PCI Express efficiency of packet transfers. In addition, it does not consider the data copy issue.
To efficiently tackle all challenges from high-speed networks, the paper proposes a new server I/O architecture, where the responsibility for managing DMA descriptors is moved to an on-chip network engine, known as NEngine. The on-chip descriptor management exposes plenty of optimization opportunities like extending descriptors. Information about data incurring memory stalls during network processing is added into descriptors.
It basically works like this: When the NIC receives a packet, it directly pushes the packet into NEngine without waiting for long latency descriptors fetches. NEngine reads extended descriptors to obtain packet destination location and information about data incurring memory stalls. Then, it moves the packet into the destination memory location and checks whether data incurring the stalls resides in caches. If not, NEngine sends data address to the hardware prefetching facility for loading the data, thus avoiding memory stalls to them during packet processing.To address the data copy issue, NEngine moves payload inside last level cache and invalidates source cache lines after the movement. Source data becomes useless and dead after the copy.
The new I/O architecture allows the DMA engine to have fast access to descriptors and keeps packets in CPU caches rather than in NIC buffers. These designs substantially reduce the burden on the DMA engine and avoid extensive NIC buffers in high-speed networks. While NICs are decoupled from DMA engine, they maintain other hardware features such as Receive Side Scaling and Interrupt Coalescing.
Unlike previous approaches such as DCA, the new server I/O architecture ameliorates all major performance bottlenecks of network processing and simplifies NIC designs, enabling general-purpose platforms to be well suited for high-speed networks. Performance evaluation shows that it significantly improves the network processing efficiency and Web server throughput while substantially reducing the NIC hardware complexity. The new server I/O architecture inherits the descriptor-based software/hardware interface and only needs some modest support from the device driver and the data copy component. There is no need to modify TCP/IP protocol stack, system calls or user applications.
About the Author
Guangdeng Liao is a fifth year Ph.D. student at University of California, Riverside. His research interest lies in high performance I/O, computer architecture and virtualization.