Moore’s Law Meets Exascale Computing
There are no exascale supercomputers yet, but there are plenty of research papers on the subject. The latest is a short but intense white paper centering on some of the specific challenges related to CMOS technology over the next decade and a half. The paper’s principal focus is about dealing with the end of Moore’s Law, which, according to best predictions, will occur during the decade of exascale computing.
Titled Exascale Research: Preparing for the Post-Moore Era (PDF), the paper is authored by HPC experts Marc Snir, Bill Gropp and Peter Kogge, who argue that we need to start using CMOS technology much more efficiently, while simultaneously accelerating the development of its replacement.
One of the tenets of supercomputing, and information technology in general, is that processors are expected to get more powerful and less expensive each year. Like the shark that needs to keep swimming to stay alive, the IT industry is based on the assumption that the hardware has to keep moving forward to support the expectations of the market.
This is certainly true for exascale proponents, who see the next level of HPC capability as a way to move forward on big science problems and help solve global challenges like climate change mitigation and the development of alternative energy sources. In the US, there is also the need to support our nuclear stockpile with compute-intensive virtual simulations — a task that is becoming increasingly difficult as the original expertise in designing and testing nuclear weapons disappears.
National security, too, has become very dependent on supercomputing. As the authors state, “In
an era where information becomes the main weapon of war, the US cannot afford to be outcomputed anymore that it can afford to be outgunned.”
It’s a given that the semiconductors behind exascale computing will, at least initially, use CMOS, a technology that’s been in common use since the 1970s. The problem is that CMOS (complementary-symmetry metal–oxide–semiconductor) is slowly giving way to the unrelenting laws of physics. Due to increasing leakage current, voltage scaling has already plateaued. That occurred nearly a decade ago when transistor feature size reached 130 nm. The result was that processor speeds leveled off.
And soon feature scaling will end as well. According to the white paper, CMOS technology will grind to a halt sometime in the middle of the next decade when the size of transistors reaches around 7 nm — about 30 atoms of silicon crystal. As the authors put it:
We have become accustomed to the relentless improvement in the density of silicon chips, leading to a doubling of the number of transistors per chip every 18 months, as predicted by “Moore’s Law”. In the process, we have forgotten “Stein’s Law”: “If something cannot go on forever, it will stop.”
And unfortunately there is currently no technology to take the place of CMOS, although a number of candidates are on the table. Spintronics, nanowires, nanotubes, graphene, and other more exotic technologies are all being tested in the research labs, but none are ready to provide a wholesale replacement of CMOS. To that end, one of the principal recommendations of the authors is for more government funding to accelerate the evaluation, research and development of these technologies, as a precursor to commercial production 10 to 15 years down the road.
It should be noted, as the authors do, that the peak performance of supercomputer has increased faster than CMOS scaling, so merely switching technologies is not a panacea for high performance computing. In particular, HPC systems have gotten more powerful by increasing the number of processors, on top of gains realized by shrinking CMOS geometries. That has repercussions in the failure rate of the system, which is growing in concert with system size.
The larger point is that the end of CMOS scaling can’t be compensated for just by adding more chips. In fact, it’s already assumed that the processor count, memory capacity, and other components will have to grow substantially to reach exascale levels, and the increased failure rates will have to be dealt with separately.
On the CMOS front, the main issue is power consumption, most of which is not strictly related to computation. The paper cites a recent report that projected a 2018-era processor will use 475 picojoules/flop for memory access versus 10 picojoules/flop for the floating point unit. The memory access includes both on-chip communication associated with cache access and off-chip communication to main memory.
To mitigate this, the authors say that smarter use of processor circuitry needs to be pursued. That includes both hardware (e.g., lower power circuits and denser packaging) and software (e.g., algorithms than minimize data movement and languages able to specify locality). More energy-aware communication protocols are also needed.
The good news is that most of the performance/power improvements discussed in the paper will also benefit the commodity computing space. But the authors also say that some of the technology required to support future HPC systems will not be needed by the volume market:
We need to identify where commodity technologies are most likely to diverge from the technologies needed to continue the fast progress in the performance of high-end platforms; and we need government funding in order to accelerate the research and development of those technologies that are essential for high-end computing but are unlikely to have broad markets.
The authors aren’t suggesting we need to build graphene supercomputers, while the rest of the world moves to spintronics. But there may be certain key technologies that can be wrapped around post-CMOS computing that will be unique to exascale computing. As always, the tricky part will be to find the right mix of commodity and HPC-specific technologies to keep the industry moving forward.