Since 1986 - Covering the Fastest Computers in the World and the People Who Run Them

Language Flags
November 17, 2011

The Bumpy Road to Exascale: A Q&A with Thomas Sterling

Nicole Hemsoth

With a number of government and commercial exascale projects in full swing, SC11 has provided a convenient venue for vendors, academics and government types to tout their vision of the future of supercomputing. There is no one better to add some perspective on the status of the various exascale work than Thomas Sterling, Professor of Informatics and Computing Indiana University, and one of the foremost experts on supercomputing architectures. We talked to him before the conference about this topic as well as his about his own work on HPC runtime software.

HPCwire: Putting aside more special-purpose microprocessor architectures, such as the latest IBM Blue Gene/Q SoC, or Fujitsu’s SPARC64 VIIIfx processor that power the K Computer, for the mainstream HPC market, it looks like the biggest performance boost will come from GPUs, Intel’s upcoming MIC coprocessor, or the on-chip integration of these accelerators with more general-purpose CPU implementations, like x86 and ARM. Do you think this is an accurate assessment or do you see other architectural possibilities developing for HPC systems over the next few years?

Thomas Sterling: This is a period of transition with wide variation in computing components and mix thereof. I believe there are two issues regarding system architecture that are not being addressed by the current techniques you have identified. One relates to the memory system where the opportunity for embedded memory processors optimized for low energy, low latency, high bandwidth access needs to be supported. The second is the need for new functionality that supports the interoperability among the potentially billion cores that may comprise an exascale class system.

Such functionality although untried can greatly diminish overhead costs thereby improving scalability. Among such functions are new mechanisms for managing the global address space, likely for future generation systems. I anticipate that future systems will mix high throughput computing elements with arrays of embedded memory processor cores tightly coupled with the arrays of memory banks. Indeed, it is the more conventional CPUs that may ultimately go extinct or at least be relegated to subservient roles.

HPCwire: Do you see these architectures evolving in such a way as to enable exascale computing by 2020 or sooner, or do you think those early exascale machines, will, by necessity be built with special-purpose microprocessors?

Sterling: I am unclear as to the ultimate path of processor core evolution. We are in an era when the optimization of future HPC systems will de-emphasize the importance of processor utilization and highlight overhead and data movement costs in both time and energy. While there will be some resistance to change from prior processor designs due to the investments made over long periods of times and many codes, even as such processors enter their twilight.

There is an important convergence between the requirements of those cores integrated in the largest machines and those in the smallest machines such as mobile embedded systems. Size, energy, reliability all are key factors in both classes of system. I expect that the constituent cores of future supercomputers. How data and metadata is manipulated in the future both to extract parallelism and to support new forms of symbolic computing will force a redirection of cores.

But there will still be problems that may benefit from special structures like signal processing, GPU, or Anton-like SPDs. So, we can expect that heterogeneous system structures will become increasingly common. But how computation will be organized and coordinated has yet to be determined and will reflect the next execution model.

HPCwire: Do you see any commercial memory technologies in the works that will support exascale computing, or just more generally, address the memory wall problem we have in HPC — for example something like the Hybrid Memory Cube technology that Micron and others are pursuing?

Sterling: The opportunity to stack memory dies with each other and with multicore dies or communication interface chips interconnected by vias directly through the silicon substrates can dramatically alter the form and function of system components. It opens new opportunities for attacking the memory wall. This may very well be one of the most promising and dramatic advances in memory technology that could have significant impact on the commercial market.

HPCwire: You attended the International Exascale Software (IESP) meeting in Germany in October. What developments were discussed there? Do you think this work is on track?

We should congratulate our colleagues like Pete Beckman, Jack Dongarra, Paul Messina, Satoshi Matsuoka, and Bernd Mohr among others for their continuing efforts to nurture an international community dedicated to a common goal of creating a shared software stack for exascale computing. This is not an easy task nor is there a clear precedent for such a worldwide initiative. Yet, without it may be impractical for HPC to get much further than about 2015.

We are already experiencing ad hoc approaches to both hardware and software resulting in unfortunate dramatic increases in programming complexity. There are two overriding issues here: 1) what is the execution model or conceptual strategy required to guide the development of such a software stack, and 2) how will the work and credit be shared among and across the international stakeholders.

The first issue has elicited a dichotomy of views between those who favor an incremental strategy from the conventional methods and tools and those who, including myself, favor a revolutionary approach to meet the challenges of exascale. The first group correctly is concerned about the potential disruptive effects of addressing exascale through a process of replacement of key system component layers. The second group is possibly — I think probably — correct in their assertion that without a paradigm shift in the manner in which computation is organized and conducted that except in a few special cases there will not be adequate efficiency or scalability to fully employ systems capable of exaflops performance by 2020.

While there is a strong dominance of those who favor the conventional incremental approach, the IESP meeting in Cologne hosted one of its three working groups on the possibilities associated with “Revolutionary Approaches.” Bronis de Supinski of Lawrence Livermore National Laboratory and I co-chaired this session that involved more than 20 self-selected participants. The findings, I think were very professional and responsible and I thank my many colleagues for their contributions to this useful set of discussions. The report from this meeting will be made available.

With respect to the second issue, it is clear that there is emerging commitment and intention in at least three arenas in the northern hemisphere to play equal peer roles. Europe intends to position itself in a leadership role with its European Exascale Software Initiative (EESI) and both China and Japan have deployed premiere platforms on the world stage. For a future approach to exascale software to work, a meaningful international engagement will have to be negotiated. This has not yet been achieved.

The Cologne meeting was focused on European efforts, interests, and directions and indeed that discussion was continued the next week at the EESI meeting in Barcelona — while invited I unfortunately had an equally important conflict back in the US. The next IESP meeting will be convened in Kyoto in April. I believe these international discussions can begin to converge on a global strategy of cooperation.

But this will not work unless there is an overriding execution model to which all parties can agree and to which all component layers, wherever developed will be compliant. Otherwise, all we will have is a software stack of Babel.

HPCwire: Back in the US, you recently attend the DOE Exascale meeting? Any new developments on that front? How would you characterize the agency’s co-design approach?

Sterling: The DOE Exascale PI meeting was well attended and engaged the time and interest of much of the HPC systems and application development community. It is apparent that DOE is assuming the leadership role in the US in the development of critical enabling technologies, both hardware and software, for the future of high performance computing across this decade culminating in sustained Exaflops prior to 2020 if possible.

Under the leadership of Bill Harrod and Dan Hitchcock of ASCR with contributions from Sonia Sachs, Lenore Mullin, and Lucy Nowels there is emerging a strong multifaceted program being instituted in close cooperation with DOE NNSA under Bob Meisner and others. It is taking advantage of the strengths of its many national laboratories across the US as well as additional contributions from academia and industry. Key to its future success is the foundation principles of co-design, runtime introspection, and cross-cutting execution models driven by mission-critical applications.

The emergent DOE co-design approach is two-tiered: the co-design of HPC systems and applications, and intra-system between the component layers comprising the systems. An emphasis on quantitative modeling and evaluation, the use of abstract machines and their simulation guided by execution models, and the validation of design through full applications and their surrogate mini-apps are defining the future methodology potentially to be employed.

Of premiere importance is the continued support of ever larger and faster DOE-relevant applications without disruption throughout the decade. But it is also preparing for a potential paradigm shift that may prove essential to achieving the quantum leap to exascale and the system development as well as that of new application algorithms that may be required to ensure US competitiveness in the exascale era.

HPCwire: I saw very little mention of DARPA’s UHPC program at the conference, although it looks like you will be addressing recent experience of that effort at your Disruptive Technology presentation at SC11 on Thursday, here in Seattle. I’ve heard rumors that the program funding has been problematic. What is the status of the effort?

Sterling: The DARPA UHPC program when inaugurated was very exciting; indeed quite possibly the most exciting program in HPC in almost a decade. It was forward looking and was unambiguously aggressive in its research directions. While not formally an exascale project, the technologies, both hardware and software, if realized would have been capable of meeting exascale capabilities with the integration of a thousand racks or less; large but not unachievable.

As I’ve mentioned earlier, the issue of cross-cutting execution models is, as they always have been, crucial to any real paradigm shift and the UHPC program adopted this as one of its foundational principles. Four exceptional projects were selected by DARPA to go forward with the first two-year phase including the X-caliber project of which I am fortunate to be a part primed by Sandia National Laboratories and led by Richard Murphy.

But as you point out, there is some question about the future of this program as DARPA, I suppose in its infinite wisdom, reconsiders its commitment to this form of future computing and its role on behalf of the security of our nation.

My opinion may not matter much but for what it is worth, I believe that leadership in HPC is essential for the welfare of the US, its defense, its base of skills, and its economy. I would like to see our leaders precede with this program that took years to organize to give the Department of Defense the cutting edge computational tools it needs in support of our men and women in uniform and the citizens of America they safeguard.

We are in a leadership position now in HPC technology. But it is much harder to play catch-up after we slip behind than maintaining our position of staying up in front. I hope DARPA sees that.
 
HPCwire: Turning back to your Disruptive Technology session, tell us a little bit about the runtime and execution model you’ll be presenting. In a nutshell, what is it about and what makes it disruptive?

Sterling: As controversial as the idea is, I believe we are facing a major paradigm shift in parallel computing to address the many new challenges that recent advances in the underlying enabling technologies impose. This has happened at least five times before in the history of HPC. We can all see clear manifestations of such advances with multicore, GPUs, and even special purpose devices.

But other signs such as low efficiencies, increasing numbers of applications that do not scale well, and multiple layers of programming models, for example, MPI+OpenMP+CUDA, are all indicators that the dominant conventional execution model, communicating sequential processes, after two decades of success is no longer serving current needs let alone providing a path to the future.

My brief presentation at the Disruptive Technology session will describe key attributes of a future execution model that may address many of these problems. The experimental ParalleX execution model integrates some prior art and a few innovative ideas to provide a new strategy — in the sense of distinguished from usual practice — for attacking current limitations in node efficiency and scalability both of which will be required to achieve practical exascale performance within this decade.

This includes critical power and reliability conditions. Exposing and exploiting new forms of parallelism, of reducing and hiding the effects of latency, minimizing control overheads, and circumventing blocking on shared physical and logical resources all need to be achieved through the concepts of a new execution model and the development of the hardware and software component layers that will fulfill its functionality. There is no magic here and many have considered similar forms at least in part of this class of computation before with some ideas going back two or three decades.

ParalleX presumes the exploitation of continuous runtime information to dynamically adjust resource management and task scheduling. It employs a global name space that extends beyond PGAS to permit the migration of virtual objects in physical space for load balancing, reliability, and energy management as well as low overhead accesses. It uses an advanced form of active messages for message-driven computing to both reduce and hide latencies through moving work to the data when appropriate and even migrating continuations across physical space to unpin control state. Lightweight sophisticated synchronization for declarative control eliminating barriers and manages asynchrony while ensuring correctness of parallel execution, at least at these points, not universally unfortunately. The ParalleX model is developing semantics for fault tolerance and energy management.

An experimental runtime system, HPX-3, has been developed at LSU by a team led by Hartmut Kaiser that demonstrates the central features of this model and is being used for extensive application experiments and system measurements.

The reason why this qualifies as a disruptive technology is that to fully benefit from its integral features will require new programming models and probably changes to future system architectures as well of course a new generation of HPC runtime systems, like HPX, to support it.

Another runtime system, SWARM, developed by ET International also exhibits many of these same principles. The question of how to migrate legacy codes to such an environment let alone how to extract superior performance for them relative to their native implementations in unknown although to achieve equality is anticipated to be possible.

Tags:

SC14 Virtual Booth Tours

AMD SC14 video AMD Virtual Booth Tour @ SC14
Click to Play Video
Cray SC14 video Cray Virtual Booth Tour @ SC14
Click to Play Video
Datasite SC14 video DataSite and RedLine @ SC14
Click to Play Video
HP SC14 video HP Virtual Booth Tour @ SC14
Click to Play Video
IBM DCS3860 and Elastic Storage @ SC14 video IBM DCS3860 and Elastic Storage @ SC14
Click to Play Video
IBM Flash Storage
@ SC14 video IBM Flash Storage @ SC14  
Click to Play Video
IBM Platform @ SC14 video IBM Platform @ SC14
Click to Play Video
IBM Power Big Data SC14 video IBM Power Big Data @ SC14
Click to Play Video
Intel SC14 video Intel Virtual Booth Tour @ SC14
Click to Play Video
Lenovo SC14 video Lenovo Virtual Booth Tour @ SC14
Click to Play Video
Mellanox SC14 video Mellanox Virtual Booth Tour @ SC14
Click to Play Video
Panasas SC14 video Panasas Virtual Booth Tour @ SC14
Click to Play Video
Quanta SC14 video Quanta Virtual Booth Tour @ SC14
Click to Play Video
Seagate SC14 video Seagate Virtual Booth Tour @ SC14
Click to Play Video
Supermicro SC14 video Supermicro Virtual Booth Tour @ SC14
Click to Play Video