Chip Simulation for the 1000-Core Era
Multicore chips have found their way into all facets of every day life. Desktops, laptops, mobile devices, servers, and supercomputers all take advantage of this technology. But, as core counts get into serious double-digit territory (i.e., the manycore realm), simulating processor designs is going to get really difficult. Researchers at MIT have come up with a software simulator to attack the problem.
Hornet is MIT’s answer to simulate the behavior of multicore and manycore processors. One of the main features of the simulator is its ability to deliver cycle-accurate results for up to 1,000 cores without the need for hardware, even FPGA-based simulators. In the paper describing Hornet’s inner workings, the researchers describe the software as “a highly configurable, cycle-level multicore simulator with support for a variety of memory hierarchies, interconnect routing and VC allocation algorithms, as well as accurate power and thermal modeling.”
The researchers go on to say that Hornet’s multithreaded simulation engine divides the work equally among the cores, allowing for either cycle-accurate precision or increased performance at some accuracy cost. In a report from Ars Technica, Srini Devadas, professor of electrical engineering and computer science at MIT reiterates that point saying, “There’s always a tradeoff between speed and accuracy.”
The software has the ability to find problems in processor designs that were previously undetectable by traditional chip simulators. For example, the Hornet researchers demonstrated how current tools are unable to detect dead-lock conditions, a flaw that Hornet was able to catch.
Devadas’ team is also working on its own manycore chip architecture, which should give Hornet more time to get its feet wet. According to him, they’re confident they can use the simulator to develop a 64-core design today. Eventually they’re aiming for a processor with 100-plus cores.
A 1,000 cores, though, seems like a real stretch today, considering most commercial CPUs are in the 4- to 16-core range. But manycore processors are already in the works. Chipmaker Tilera is building 100-core CPUs today, and Intel’s upcoming Knights Ferry MIC coprocessor is expected to top 50 cores.
Given Moore’s Law and its exploitation by commercial chipmakers, it’s not inconceivable to expect manycore processors within the decade. Tools like Hornet look to make the development of these designs, if not easy, at least more manageable.