April 12, 2012

Hopping Off the Bus

Robert Gelber

As processor core counts rise, MIT research suggests on-chip networks will be needed.

An announcement from MIT discusses research that proposes to replace the traditional communication bus on processors with an on-chip network. The report explains why such an arrangement is much better for multicore, and especially manycore, architectures:

Today, a typical chip might have six or eight cores, all communicating with each other over a single bundle of wires, called a bus. With a bus, however, only one pair of cores can talk at a time, which would be a serious limitation in chips with hundreds or even thousands of cores.

Li-Shiuan Peh, an associate professor of electrical engineering and computer science at MIT, delivered more dismal news about the scalability of the bus architecture. Her research shows that this architecture only scales to around 8 cores, pointing to many 10-core chips that utilize a second bus. She explains the loss of efficiency is related to the fact the buses consume a lot of power, because they have to drive data across long wires to lots of cores at the same time.

Last summer, Peh and her colleagues presented a paper at the Design Automation Conference in which they discussed the efficiency of an on-chip network and demonstrated the performance using a test processor. Instead of using an all-to-all connection, each core only connects to its nearest neighbors using on-chip routers, thereby reducing power requirements and increasing the scalability of the architecture.

The downside is that data from each core has to pass through each subsequent core router along the way to its final destination. Also, if two packets of data show up at a particular router at the same time, one packet has to be saved while the other one is being processed.

Despite such challenges, some manufacturers have already hopped off the bus. San Jose-based chipmaker Tilera, for example, employs an on-chip network in their manycore architecture. They currently offer 32 and 64-core processors and look to scale beyond 100 cores in the near future.

Intel also seems to be in on the trend. The company’s research lab has produced an experimental, 48-core processor named the “Single-chip Cloud Computer” (SCC). Although that’s just a plaything for researchers, the commercialization of Intel’s manycore MIC architecture, along with the recent acquisition of QLogic InfiniBand, could mean an on-chip network will soon be showing up on an x86 processor in the not-to-distant future.


Peh’s research suggests the bus architecture may be on its way out as processors delve into double-digit core territory. If research like that spurs chip vendors to design and build viable on-chip networks, it could usher in a new era of highly scalable processors. 

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