June 11, 2012

Intel Releases Knights Corner ISA, Lays Groundwork for MIC Launch

Michael Feldman

<img style="float: left;" src="http://media2.hpcwire.com/hpcwire/knights_corner_chip.jpg" alt="" width="99" height="78" />Intel has released a partial software stack for Knights Corner, the company's first commercial chip based on its Many Integrated Core (MIC) architecture. Also released were a number of documents describing the processor's micro-architecture, including the Knights Corner Instruction Set (ISA) Manual, which will help toolmakers and application developers build software for the upcoming chip.

Intel has released a partial software stack for Knights Corner, the company’s first commercial chip based on its Many Integrated Core (MIC) architecture. Also released were a number of documents describing the processor’s micro-architecture, including the Knights Corner Instruction Set (ISA) Manual, which will help toolmakers and application developers build software for the upcoming chip. The newly released information was described in a couple of blog posts last week by James Reinders, Intel’s chief evangelist and director of marketing for the company’s software development portfolio.

Up until now, Intel had not shared this software or documentation with anyone outside of its partner network. That posed something of a problem for third-party developers who don’t have that relationship with the Intel, but are looking to get MIC software products out the door in time for the upcoming Knights Corner launch. That chip is expected to go into production sometime in late 2012 or early 2013. Giving this first MIC product a running start is crucial, since it going to be competing against a GPU computing ecosystem with a five-year head start and an already-established product portfolio.

The newly released software from Intel includes source modifications for Linux, the GCC compiler and the GDB debugger, as well as new MIC drivers, which, together, will allow developers to build a Linux OS kernel capable of running on the manycore coprocessor. In this case, that applies to the current Knights Ferry prototype hardware, which is currently being used as a development platform at a number of sites, as well as the future Knights Corner chips.

Embedding an operating system on a coprocessor might seem a bit exotic since usually the host CPU, alone, runs the OS. But since the MIC architecture is essentially a variant of a Pentium CPU, it’s quite capable of acting as its own host. That will allow the Knights Corner to behave as a peer to the CPU, rather than just its slave. How that gets used in practice is still up in the air, but it would certainly make for a more flexible development environment, inasmuch as entire Linux apps could be launched and controlled locally on the MIC chip.

Even though this software is now public, the mods still have to work their way into the various Linux, GCC and GDB distributions, which could take awhile. In the meantime, anyone with a Knights Ferry test setup or simulator can pick up the new code on Intel’s MIC software resource page and have at it.

It’s important to note that the current set of mods delivered last week does not include MIC application support, which would have to encompass GCC and GDB support for the Knight Corner vector instructions. (The Linux kernel running on the coprocessor has no need for vector instructions.) That means for the time being, developers will still have to rely on Intel’s own compilers (or a CAPS enterprise compiler that is hooked into the Intel MIC back-end) if they want to build Knights Ferry or Knights Corner applications.

Also left out is compiler support for any coprocessor offload directives (text that can be inserted into high-level source that tells the compiler to execute specific code on the accelerator). Intel has not endorsed OpenACC, the budding accelerator directives standard backed by NVIDIA and some of its partners (PGI, CAPS enterprise, and Cray). Instead it has invented its own offload technology, known as LEO (Language Extensions for Offload), which users of the Intel compiler can tap into to offload chunks of their application onto the MIC hardware.

LEO is a less restrictive and more generalized set of offload directives than OpenACC since its allows the programmer to offload virtually any function or even a whole application to the MIC hardware. Remember that MIC is based on the Pentium, an older Intel architecture chosen for its simpler design, which is more suitable for a manycore throughput processor. Although the individual cores are relatively slow, they have almost all the functional capabilities of Xeon cores. Thus MIC can behave as a general-purpose CPU, albeit one with limited single-thread performance and smaller memory.

In any case, LEO will likely never become a public standard on its own. The end game for Intel is to get its capabilities incorporated into OpenMP’s future extension for accelerator directives. That effort will somehow have to blend the more GPU-oriented OpenACC standard with the CPU-oriented LEO model and come up with a platform-independent standard that can be applied across all types of accelerators.

Although the MIC software stack that Intel donated last week didn’t do much for application developers, the documentation that was made public should help them, at least indirectly. In addition to the Knights Corner ISA manual, the chip maker also provided the ABI (Application Binary Interface) and Performance Monitoring Unit documents. With this documentation in hand, software tool makers now have the information needed to build their own MIC compilers, libraries and other developer gadgets like debuggers and simulators. All the docs are available for download on the MIC resources page mentioned above.

The ISA and the ABI documents are more like addendums to the standard IA versions since MIC itself is just an x86 variant. MIC, though, overlays 64-bit processing, extra wide vector instructions, and a manycore design on top of the original Pentium architecture, which makes it a unique IA64 processor family.

Not surprisingly, most of the ISA doc focuses on the 512-bit wide vector instructions, along with all the fancy vector masking and shifting that turns the new chip into a SIMD powerhouse. MIC’s vector width is twice that of AVX (256 bits), the SIMD instruction set in the latest Intel Sandy Bridge and AMD Bulldozer CPUs. AVX, in turn, doubled the 128-bit wide vectors available in the previous SSE vector units.

Although the ISA is intended to grease the wheels for third-party MIC software tools, the information can also be used by application developers who are looking to access MIC instruction directly via intrinsics (assembly instructions that can be inserted into high level source code). With the intrinsics, bare-metal programmers can tap directly into the hardware to eke out maximum performance.

Now that some of the software and supporting docs are in the public domain, Intel will be able to work more openly with MIC developers and third-party toolmakers. All of this should help to jumpstart the ecosystem in preparation for the upcoming Knights Corner launch, which is only about half a year away. At the International Supercomputing Conference (ISC’12) next week in Germany, we should get a much better sense of how far along Intel is with its MIC rollout.

Share This