Andy Bechtolsheim Lays Out Future of Datacenter Fabrics
The acceleration of Ethernet performance over the past few years and its subsequent entry into world of datacenter fabrics is changing the landscape of high performance interconnects. At the recent Linley Tech Processor Conference, networking sage Andy Bechtolsheim talked about the how he sees the technology playing out over the next decade.
An EE Times article, penned by Rick Merritt, covered Bechtolsheim’s conference presentation in nice detail and is worth a read. Bechtolsheim’s main themes encompassed everything from network buffer sizes to the changing economics of the switch-making business.
The divergence between the breakneck pace of transistor shrinkage (Moore’s Law) and the more leisurely performance increase in I/O bandwidth. According the Bechtolsheim, while chips are doubling their transistor density ever couple of years, network bandwidth is only doubling every four years.
To take up the slack, he said, network protocols and applications have to be optimized. In lieu of that, network switch design has to be improved, which to Bechtolsheim is all about right-sizing buffers.
The networking guru decries the proliferation of optical interconnect standards in the pipeline that are ostensibly being developed to deal with the upcoming 100GbE networks. Bechtolsheim thinks the five standards in motion today are just too many.
Nevertheless, he’s bullish on Ethernet technology, and the switch biz, in general — not too surprising considering the amount of time and money he has devoted to Arista, his Ethernet switch startup. Bechtolsheim notes that the current boom in datacenter buildout is fueling a lot of networking growth, which is projected to triple the switch market from $4-5 billion in 2010 to $15 billion by 2015.
He also notes that economics is forcing everyone to use merchant chips, as Arista does now, and even network behemoths like Cisco won’t be able to afford custom ASICs for their own switches. That will likely shrink the number of such vendors to just a handful over the next few years. Regardless, he says, chip design will be the critical technology for the networking business going forward.
Full story at EE Times