November 12, 2012

Intel Brings Manycore x86 to Market with Knights Corner

Michael Feldman

<img style="float: left;" src="" alt="" width="98" height="85" />Intel Corp. officially made its entry into the manycore realm today as it debuted "Knights Corner," the company's first Xeon Phi coprocessor. The new products clock in at just over a teraflop, double precision, setting the stage for an HPC accelerator battle that will pit Intel against GPU makers NVIDIA and AMD. Both of those companies also released their latest HPC accelerators into the wild earlier today at the annual Supercomputing Conference in Salt Lake City.

Intel Corp. officially made its entry into the manycore realm today as it debuted “Knights Corner,” the company’s first Xeon Phi coprocessor. The new products clock in at just over a teraflop, double precision, setting the stage for an HPC accelerator battle that will pit Intel against GPU makers NVIDIA and AMD. Both of those companies also released their latest HPC accelerators into the wild earlier today at the annual Supercomputing Conference in Salt Lake City.

The 22nm Knights Corner chips will initially be going into two Xeon Phi products: the 3120A and 5110P, both of which are PCIe cards outfitted with a single coprocessor and several gigabytes of GDDR5 memory. A pre-production part, the SE10P, is also in circulation, but will not be generally available.

FLOPS-wise, the two cards are rather similar. The 3120A delivers 1.003 double precision teraflops with 60 cores (1.053 GHZ), while the 5110P offers a skosh more, at 1.011 teraflops, but does so with just 57 cores that are clocked somewhat higher (1.1 GHz). The big difference is memory. The 5110P houses 8 GB and delivers 320 GB/sec of peak bandwidth; the 3120A, comes with 6 GB and 240 GB/sec of bandwidth.

The memory gap between the two cards defines their different application targets. The 3120A is aimed at compute-bound workloads, where the data can be keep locally on the card or, better yet, in on-chip cache. That makes it the device of choice for many applications in financial services, life sciences, and codes that rely a lot on linear algebra calculations.

For applications that lean more toward the data-intensive side of the spectrum, or that rely on streaming data, Intel will point you to the 5110P. There, the higher memory capacity and bandwidth will be better for apps like digital content creation, seismic modeling, and ray tracing.

There’s a significant difference in power consumption too. The 5110P draws 225 watts at peak load, while the 3120A is rated at 300 watts, which is going to limit its deployment in densely configured servers. Nevertheless, Intel says this latter card is the go-to product for situations where you want to maximize FLOPS per dollar. Intel’s recommended price is below $2,000 for this part, while the higher memory 5110P is being targeted at $2,649.

The two product also differ in cooling regimes. The P in the 5110P means it’s a passively cooled card, which is more convenient for servers, especially denser set-ups that are all the rage these days in HPC. The 3120A is actively cooled, so it would be more applicable to less densely configured servers and workstations. Intel also intends to offer a passively cooled 3100 part at some point.

The 5110P is shipping today, with general availability on January 28. The 3120A is scheduled for availability sometime in the first half of 2013.

The aforementioned SE10P has also been shipping for a while to satisfy early customers, namely TACC (The Texas Advanced Computing Center), for its 10-petaflop Stampede supercomputer. Stampede is already up and running, but apparently not at full capacity. The Linpack submission for the TOP500 had it at 4 peak petaflops (2.6 petaflops Linpack), which is less than half it’s final  FLOPS level.

According to Intel, the SE10P has essentially the same feature set as the 5110P, but it runs at 300 watts and with about 10 percent better peak memory bandwidth. As mentioned before, this part is not slated for general production, so it’s possible that the remainder of Stampede will be built out with the 5110P, or perhaps some other yet to be announced Xeon Phi.

Because the SE10P has been available for awhile, a lot of the benchmarks Intel is initially touting (including the ones mentioned here), are based on this card. The other two products shouldn’t be too far off though, especially the 5110P. For Linpack, Intel has clocked this pre-production part at 803 teraflops and DGEMM (double precision matrix multiply) at 883 teraflops, and SGEMM (single precision matrix multiply) at 1,860 gigaflops. STREAM Triad, which measures memory performance, checks in at 181 GB/sec with error correction (ECC) off and 175 GB/sec when it’s on. All those results are between two to three times better than that delivered by a 2-socket server equipped with Xeon E5-2670 (Sandy Bridge) CPUs.

In fact, Intel is telling customers that for parallel applications that can take advantage of the Xeon Phi’s vector capabilities, codes will generally see a 2X to 3X speedup when you drop in a Knights Corner coprocessor. For example, the chipmaker is reporting a 2.53X performance bump for a seismic imaging code, 2.52X for molecular dynamics, 2.27X for lattice QCD, 1.7X for a finite element solver, and 1.88X for ray tracing. There are a few outliers for certain single-precision financial codes: 10.75X for Black Scholes and 8.92X for Monte Carlo, thanks mainly to on-chip support for transcendental functions in the Xeon Phi platform.

Overall though, Intel is promising 2X to 3X speedups, and only for software that lends itself to parallelization and vectorization. According to Joe Curley, Intel’s director of marketing for the Data Center Group, that entails a relatively small portion of HPC applications. “But,” he says, “customers who have those applications are motivated to find ways to get performance breakthroughs.”

Intel has to thread the needle here. It can’t tout the Xeon Phi at the expense of its mainstream Xeon CPUs. The idea is to speed up applications or portions of applications that are out of reach for straight Xeons. But the chipmaker wants to sell you both products — one for maximizing single-threaded codes, the other for highly parallel, vector-intensive ones. That’s not really different from how NVIDIA has positioned its GPU accelerators relative to CPUs.

NVIDIA, though, is more aggressive about pointing to big performance increases over CPU-only platforms, more on the order of 5X to 30X and beyond. For its new K20X Tesla part announced earlier today, the GPU-maker is claiming a 7X performance advantage over to a Sandy Bridge Xeon. Although that makes it seem like the GPU competition is three times faster than Knights Corner, the NVIDIA comparison is GPU-to-CPU, while Intel prefers to match its coprocessor against two Xeons.

Nevertheless, NVIDIA’s K20 does top Knights Corner in both raw performance and performance per watt. The 235 watt K20X offers 1.31 double precision teraflops, while the 225 watt 5110P, at 1.011 teraflops, delivers 300 gigaflops less. Advantage NVIDIA.

It appears to be even more skewed for single precision FLOPS, where the K20X offers three times its double precision performance; for the Knights Corner, single precision appears to be just twice that of its double precision results.

On the other hand, the 5110P is top in memory capacity and bandwidth. At 8 GB and 320 GB/sec, respectively, this Knights Corner part outruns the K20X’s 6 GB and 250 GB/sec by a wide margin. For codes that are more data-bound than compute-bound, that could be a decided advantage.

But Intel believes its biggest hammer against GPUs is its programming environment. It allows developers to use the same Intel parallel compilers, libraries and tools they are using for their Xeon codes. Third-party development tools from CAPS enterprise, PGI, Rogue Wave, Allinea, NAG, and others also now include Xeon Phi support.

Intel also likes to point out that GPUs are best at speeding up data parallel apps, and a number of HPC applications do not map very well to that model. “An awful lot of scientific programs really don’t tolerate some of the limitations of explicit data parallelism,” Curley told HPCwire. “Codes can branch; codes can have a great deal of recursion in them; codes can be self-modifying; codes can use sparse irregular data sets. All of which can become vexing for explicitly data parallel architectures, and all of which run on the Intel Xeon Phi.”

That’s not to say it will be a snap to create high-performing Xeon Phi codes. You may be able get applications up and running in a matter of days via some simple code tweaks and a recompilation, but Xeon Phi represents a true throughput accelerator design, and trying to treat it as a manycore CPU, as Intel has sometimes implied, will probably not lead to accelerated applications.

The proof will be in the application pudding. At this point, NVIDIA and the CUDA faithful have a six-year head start in porting codes to HPC accelerators. Intel, though, is a force to be reckoned with, so if the chipmaker can garner enough enthusiasm on the software side, it could make up for lost time rather quickly.

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