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November 20, 2012

Texas Instruments Puts ARM-DSP Processors Into Play for HPC

Michael Feldman

NVIDIA, Intel and AMD were not the only chip vendors unveiling new HPC accelerators last week SC12. Texas Instruments (TI) announced a set of heterogeneous processors that they believe will offer among the best performance per watt in the industry. In this case, the chipmaker glued an ARM CPU and digital signal processor (DSP) together on the same die, offering a low-power SoC with an impressive number of FLOPS.

This represents TI’s second attempt to push a wedge into the high performance computing space. The company made its initial foray into the market in October 2011 when it introduced its multicore Keystone DSPs (TMS320C66x). The primary destination of those chips was 4G cellular base stations and radio network controllers, but since floating point functionality had to be added to serve that market, TI felt the same silicon could double as HPC accelerators.

One of the problems with the standalone DSP devices being used for HPC was that the application kernels had to be offloaded from a CPU host to the DSP. That wasn’t because the DSPs couldn’t run a whole application (the DSP is closer to a manycore CPU than a GPU), but because there was no Linux OS or MPI library ports for the architecture. ARM, though, had support for both of these pieces of software, allowing developers to use a traditional driver-accelerator model.

There are actually six new SoCs being introduced by TI, two of which are ARM-only (no DSP integration) that are aimed at powering routers, switches, wireless appliances, and other networking devices. The four remaining parts are the ARM-DSP heterogenous chips. These heterogeneous chips are fully tricked-out SoCs, with an ARM Cortex A15 CPU, a Keystone DSP, a shared memory controller, an integrated fabric and an I/O interface. The fabric itself is a custom design from TI, known as TeraNet, which delivers a low latency, multi-terabit/second fabric that connects the ARM CPU, DSP and memory controller.

Of the four heterogeneous, two are high-end parts – the 66AK2H06 and 66AK2H12 – targeted to high performance computing, as well as media processing, video analytics, gaming, VDI, and radar. The 66AK2H12 4-core ARM/8-core DSP is the more powerful of the two. It offers 198 gigaflops of single precision (SP) floating point performance or 70 gigaflops in double precision. That includes the DSP floating point as well as the Neon FP unit in the ARM CPU.

Although, this ARM-DSP SoC represents only about half the FLOPS of a high-end x86 CPU, the TI chip delivers this in about one-tenth the power – 13 to 14 watts. For single precision, that works out to about 16 SP gigaflops per watt, which is about the same as last year’s stand-alone 8-core DSP chip, sans CPU. It’s also nearly as good as latest NVIDIA’s K10 Tesla part, which delivers about 20 SP gigaflops per watt.

Since the ARM CPU is 32-bit architecture, memory reach for these chips is limited. In fact, each SoC can only access up to 16 GB – not much compared to standard x86 CPU, but about twice as much as a traditional accelerator. The hetero chips, though, don’t need an external CPU to feed it, as the K10 does; the on-chip ARM serves as the host driver. This eliminates the PCIe communication overhead of a CPU hooked to an discrete accelerator.

And since the ARM and DSP units share some of the same memory, it can at least potentially simplify programming of these devices. In that sense, it’s closer to AMD’s Fusion (or APU) architecture, which glues an x86 CPU and GPU onto the same die. At this point though, the AMD offerings are being targeted for client devices, such as laptops, rather than servers.

TI is actually not making so much of a distinction in where their chips will end up. According to Arnon Friedmann, TI’s business manager for the multicore processors unit, the same SoCs targeted for servers could also be applied to embedded devices. For example, a sensor network of cameras doing video surveillance could use an ARM-DSP chip to do some local image processing; the output of which could then be shunted to a server farm of these same chips to perform deeper analytics on the pre-processed video.

“That’s a level of scalability that we think our devices bring, which others in HPC don’t offer today,” Friedmann told HPCwire. “So if you look at NVIDIA [GPUs] and Intel MIC, there really aren’t cut-down versions of these really high performance devices and they’re not quite as geared for embedded as we are.”

For HPC-type developers, TI offers both OpenMP and MPI. The chipmaker also has an alpha version of OpenCL that supports an ARM CPU that can work in conjunction with the on-chip DSP. Down the road, TI is looking to support the newly hatched OpenMP accelerator directives, which are expected to be officially codified in the standard sometime next year.

As with the other accelerators from NVIDIA, Intel and AMD vying for HPC business, the success of the TI parts will depend upon how easy they are to program and how much application performance ensues. Regarding the latter, there is already some encouraging news. According to Friedmann, an FFT kernel from an aperture radar code produced performance on par with that of a GPU, but when they moved the entire application to the chip, performance was boosted 8-fold. Friedmann says interested parties are looking to do similar ports for even larger applications.

Right now, the chipmaker is trying to bring in more HPC users to move their MPI codes over to their ARM-DSP SoCs in order to drum up interest from server makers to build hardware. In the meantime, for do-it-yourselfers, TI’s two SoCs aimed at HPC are available for sampling now. Broader availability is expected in the first quarter of 2013, with general availability of evaluation modules coming in the second quarter.

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