Since 1986 - Covering the Fastest Computers in the World and the People Who Run Them

Language Flags
December 6, 2012

The New Breed of Accelerators from NVIDIA, Intel and AMD Square Off

Michael Feldman

With the recent introduction of Intel’s first Xeon Phi coprocessors, NVIDIA’s latest Kepler GPUs, and AMD’s new FirePro S10000 graphics cards, the competition for HPC chip componentry has entered a new phase. The three chipmakers have taken somewhat different paths, though, and it will be up to the market to decide which vendor’s approach will win the day.

It is tempting to think that there might be room for all three accelerator designs in the market, but as it stands today that’s unlikely. The HPC space is too small and homogeneous to support that much architectural diversity. Just consider how the CPU side has, for the most part, consolidated to a single ISA (the x86), and to a large degree, a single vendor (Intel). While there may be a case to be made that these accelerators can offer different advantages for different applications, in their current incarnation they all are built principally as vector accelerators for CPU hosts.

That implies that the chip design that does that best, that is, delivers the most application FLOPS per dollar and per watt, will be the HPC consumer’s top choice – unless you believe that one or the other of these platforms will be substantially easier to program than the others. We’ll get to that particular aspect in a moment.

First though, it’s worthwhile just looking at the specs for the three accelerators. All of them offer teraflop-plus double precision performance with several gigabytes of ECC memory, but not all with the same power draw. And it’s the performance-per-watt that is most likely to become the driving criteria for many HPC users as they try to squeeze maximum FLOPS from a static datacenter power supply.

The NVIDIA Tesla K20X is the one to beat in this regard. It offers 1.3 teraflops in a 235 watt package – so 5.6 gigaflops/watt. Intel’s new “Knights Corner” Xeon Phi, the 5110P, delivers 1.011 teraflops with a TDP of 225 watts, which works out to 4.5 gigaflops/watt. The AMD FirePro S10000 card that sports two “Tahiti” GPUs, is rated at 1.48 teraflops. But the FirePro draws 375 watts, so its 3.9 gigaflops/watt is actually the lowest of the bunch.

The FirePro does somewhat better in the single precision FP department, delivering 15.8 gigaflops/watt to the K20X’s 16.8 gigaflops/watt and the 5110P’s 9.0 gigaflops/watt (estimated). But if you’re really focused on single precision performance, the go-to device is the NVIDIA K10, which delivers over 20 gigaflops/watt.

Memory-wise, the Intel 5110P is tops with 8 GB and 320 GB/sec of bandwidth. The K20X is supplied with 6 GB and 250 GB/sec, so less capacity, but with roughly the same bandwidth per byte. The new FirePro is also equipped with 6 GB, but at 450 GB/sec, offers considerably more bandwidth. That’s all with ECC turned off, though, so your actual mileage will vary depending on the error correction smarts on each of these platforms.

It’s not surprising that NVIDIA’s silicon specs out so well here. They’ve been the dominant player in the accelerator business for the last several years and have spent a lot of time designing the devices for this role. But the hardware alone will not be the sole determinant. Porting applications to these accelerators and getting them to draw on those abundant FLOPS will be the biggest challenge.

It is here that Intel believes it has an advantage. The company’s line has been that existing programs, using just standard MPI and OpenMP as the framework for parallelism, will port to the Xeon Phi platform with a simple recompile and link. And while that’s true, that doesn’t necessarily guarantee good performance. In fact, it is more than likely that porting applications that lend themselves to vector acceleration on Xeon Phi will have to be modified in ways not so different than what is done for GPUs – namely splitting the code across the CPU and accelerator, such that performance is optimized across the serial and parallel parts of the application.

Until there are a number of well-known HPC applications running on the Xeon Phi, proof of easy porting with impressive performance are just claims. And in any case, OpenMP’s new accelerator directives are supposed to level the software playing field across all these platforms – at least with regard to a standard high-level software framework. As of today, though, that standard has not been ratified and it’s not clear if GPUs will be supported adequately on the initial go-around, which, given the current accelerator landscape, sort of defeats the purpose for a hardware-independent API.

This is just the beginning of the accelerator era of high performance computing, or perhaps more accurately, the end of the beginning. Especially with Intel’s entrance into the space, the accelerator model for high performance computing has been legitimized in a way that NVIDIA could not have done on its own. And while accelerators are not the be-all and end-all of HPC, right now they are driving much of the rapid performance gains we see in the industry.

That means the stakes are high for all three vendors. Whoever comes out on top is likely to establish itself as the dominant supercomputing chipmaker for the latter half of the petascale era and the first part of the exascale era, when the technology will almost certainly be integrated into the CPU die. With Intel, NVIDIA and AMD now focusing more interest in their accelerator lines, we’re apt to see an even more rapid evolution of the hardware and the software.