Fair Pricing Key to Node Sharing in HPC

By Alex Breslow, University of California San Diego

November 13, 2013

In HPC systems, jobs almost never share compute nodes. Each user requests the number of physical machines that they need to run their job, and then they run it in isolation.

While this practice was clearly the best choice for distributed applications in the pre-multi core era, the same is not necessarily true for the compute nodes of today, which integrate tens to hundreds of cores. Instead, distributed application co-location, whereby multiple parallel codes share the cores on sets of compute nodes, is a pragmatic choice for those seeking to optimize machine performance and power efficiency.

A previous study we did demonstrated co-locating pairs of 1024 process MPI jobs across 2048 cores decreases the run time of most applications and thus improves system throughput and energy efficiency by 10 to 20%.

Figure 1: An example of running 2 two-node jobs in isolation versus co-located: Switching from isolation (left) to co-location (right), where each socket is divided between applications improves system performance and energy efficiency.
Figure 1: An example of running 2 two-node jobs in isolation versus co-located: Switching from isolation (left) to co-location (right), where each socket is divided between applications improves system performance and energy efficiency.

However, not all applications benefit from distributed co-location: a significant number do slow down due to contention from their co-runners. While this slowdown is almost universally offset by gains in the performance of the co-running applications, and therefore still results in improved throughput, it causes an unfair inequity in pricing.This unfairness arises from the typical HPC accounting policy, which charges users proportionally to application run time. An example of this pricing unfairness is shown in Figure 2.  The plot shows the price a user running the GTC code would expect to pay when their job is co-run with each of the applications on the x-axis.  Under the current pricing model, the user would pay 60% more when their job is co-run with MILC instead of with AMG.

Figure 2: The current pricing mechanism (SOP) penalizes the user for co-locating their job by charging them more when their job degrades more.
Figure 2: The current pricing mechanism (SOP) penalizes the user for co-locating their job by charging them more when their job degrades more.

In this current pricing scheme, the user not only suffers from a decrease in utility caused by the increased job run time, but also faces an additional associated surcharge.  Our work, published and to be presented at SC’13 as one of the best paper candidates, targets this problem and introduces contention-aware fair pricing, where a user pays progressively less and less as their job is degraded more and more.

However, implementing such a policy is a challenge, as it requires a non-intrusive mechanism that precisely quantifies individual application degradation caused by co-running applications.  While previous work has employed offline profiling techniques to determine this degradation, we argue that such techniques are not always practical in a production setting, where online application behavior can significantly deviate from offline characterizations [3-6].  Instead we need a dynamic, lightweight, runtime system or OS service to detect such contention.

To satisfy these objectives, we have developed a low-overhead daemon, the Persistent Online Precise Pricing Agent (POPPA).  POPPA uses a fine-grain precise pricing shutter, a novel mechanism capable of measuring contention between applications with less than 1% overhead and with a mean absolute prediction error of 4%.  The shutter mechanism works by alternating the execution environment of each application between one where contention from co-runners is present, and one where it is effectively absent.  POPPA achieves this by cyclically pausing all but one application in a round-robin fashion and measuring the spike in the performance of the lone running application versus when it was co-located.

Figure 3: POPPA alternates application execution between isolation and co-location.  P and S are tunable parameters.
Figure 3: POPPA alternates application execution between isolation and co-location. P and S are tunable parameters.

The above shows the mechanism in action.  During the first phase, the POPPA daemon is dormant and threads from both applications execute.  Next, the instructions per cycle (IPC) of each application is derived from measurements taken using the hardware’s performance monitoring unit.  Then Job B is put to sleep, and the IPC of the Job A is measured.  Then Job B is woken up, and the IPC of both applications is measured.  This process then repeats but with Jobs A and B switching roles.

The POPPA daemon is fully parameterizable to allow for machine- and application-specific tradeoffs. In particular, we can configure the length of the periods between shutter events, the length of the shutter time, as well as the length for pre- and post-shutter measurements. Since each shutter requires all applications but one to sleep, the sleeping applications cannot make progress and thus lose performance during the shutter, which results in run time overhead.  By controlling the ratio between shutter time and shutter interval, this overhead can be carefully tuned to an acceptable value.  For our work, we decided on a shutter interval of 200 ms and a shutter length of 3.2 ms, as these values offered high prediction accuracy while keeping the average overhead under 1%.

This mechanism allows POPPA to be highly accurate, with a mean absolute error of 4%. The low prediction error stems from the fact that the system does not rely on a single measurement for determining degradation estimates, but rather can base its analysis on hundreds to thousands of fine-grain measurements that are uniformly spaced throughout the execution of each co-running application.  As a result, POPPA detects phase-level behaviors in applications that allow it to construct more accurate prediction estimates.

Based on these predictions, we then implement a fair pricing strategy and discount the user relative to their predicted degradation due to co-runner interference.  Our philosophy is that when a user’s application is degraded by 20%, the simplest and most intuitive pricing policy is to discount that user by 20%.  This policy allows the user to easily reason about how they will be priced and to also reap the benefit of a discount, which directly compensates for the additional time taken to run their job.  This compensation encourages users to embrace co-location, as the discounts allow their resource allocation to go further.

The art of precise and fair pricing is a key for designing future, agile, software systems and opens the door to new ways to utilize the rising class of multi- and many-core nodes.  If this article has piqued your interest, we invite you to our talk at the SC’13 conference (Title: “Enabling Fair Pricing on HPC Systems with Node Sharing”, to be presented on November 20th at 10:30AM in rooms 401/402/403). The contact author for this work is Alex Breslow, PhD student at the University of California San Diego.  Ananta Tiwari and Laura Carrington are research scientists at San Diego Supercomputer Center, Martin Schulz is a computer scientist at Lawrence Livermore National Laboratory, and  Lingjia Tang and Jason Mars are assistant professors in the University of Michigan EECS Department.

See Also:

 Cache pirating: Measuring the Curse of the Shared Cache. In Parallel Processing (ICPP)

Quantifying Effects of Shared On-chip Resource Interference for Consolidated Virtual Machines

Bubble-up: Increasing Utilization in Modern Warehouse Scale Computers via Sensible Co-locations

Managing Performance Interference Effects for QoS-Aware Clouds

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industry updates delivered to you every week!

2024 Winter Classic: Meet Team Morehouse

April 17, 2024

Morehouse College? The university is well-known for their long list of illustrious graduates, the rigor of their academics, and the quality of the instruction. They were one of the first schools to sign up for the Winter Read more…

MLCommons Launches New AI Safety Benchmark Initiative

April 16, 2024

MLCommons, organizer of the popular MLPerf benchmarking exercises (training and inference), is starting a new effort to benchmark AI Safety, one of the most pressing needs and hurdles to widespread AI adoption. The sudde Read more…

Quantinuum Reports 99.9% 2-Qubit Gate Fidelity, Caps Eventful 2 Months

April 16, 2024

March and April have been good months for Quantinuum, which today released a blog announcing the ion trap quantum computer specialist has achieved a 99.9% (three nines) two-qubit gate fidelity on its H1 system. The lates Read more…

Mystery Solved: Intel’s Former HPC Chief Now Running Software Engineering Group 

April 15, 2024

Last year, Jeff McVeigh, Intel's readily available leader of the high-performance computing group, suddenly went silent, with no interviews granted or appearances at press conferences.  It led to questions -- what's Read more…

Exciting Updates From Stanford HAI’s Seventh Annual AI Index Report

April 15, 2024

As the AI revolution marches on, it is vital to continually reassess how this technology is reshaping our world. To that end, researchers at Stanford’s Institute for Human-Centered AI (HAI) put out a yearly report to t Read more…

Crossing the Quantum Threshold: The Path to 10,000 Qubits

April 15, 2024

Editor’s Note: Why do qubit count and quality matter? What’s the difference between physical qubits and logical qubits? Quantum computer vendors toss these terms and numbers around as indicators of the strengths of t Read more…

MLCommons Launches New AI Safety Benchmark Initiative

April 16, 2024

MLCommons, organizer of the popular MLPerf benchmarking exercises (training and inference), is starting a new effort to benchmark AI Safety, one of the most pre Read more…

Exciting Updates From Stanford HAI’s Seventh Annual AI Index Report

April 15, 2024

As the AI revolution marches on, it is vital to continually reassess how this technology is reshaping our world. To that end, researchers at Stanford’s Instit Read more…

Intel’s Vision Advantage: Chips Are Available Off-the-Shelf

April 11, 2024

The chip market is facing a crisis: chip development is now concentrated in the hands of the few. A confluence of events this week reminded us how few chips Read more…

The VC View: Quantonation’s Deep Dive into Funding Quantum Start-ups

April 11, 2024

Yesterday Quantonation — which promotes itself as a one-of-a-kind venture capital (VC) company specializing in quantum science and deep physics  — announce Read more…

Nvidia’s GTC Is the New Intel IDF

April 9, 2024

After many years, Nvidia's GPU Technology Conference (GTC) was back in person and has become the conference for those who care about semiconductors and AI. I Read more…

Google Announces Homegrown ARM-based CPUs 

April 9, 2024

Google sprang a surprise at the ongoing Google Next Cloud conference by introducing its own ARM-based CPU called Axion, which will be offered to customers in it Read more…

Computational Chemistry Needs To Be Sustainable, Too

April 8, 2024

A diverse group of computational chemists is encouraging the research community to embrace a sustainable software ecosystem. That's the message behind a recent Read more…

Hyperion Research: Eleven HPC Predictions for 2024

April 4, 2024

HPCwire is happy to announce a new series with Hyperion Research  - a fact-based market research firm focusing on the HPC market. In addition to providing mark Read more…

Nvidia H100: Are 550,000 GPUs Enough for This Year?

August 17, 2023

The GPU Squeeze continues to place a premium on Nvidia H100 GPUs. In a recent Financial Times article, Nvidia reports that it expects to ship 550,000 of its lat Read more…

Synopsys Eats Ansys: Does HPC Get Indigestion?

February 8, 2024

Recently, it was announced that Synopsys is buying HPC tool developer Ansys. Started in Pittsburgh, Pa., in 1970 as Swanson Analysis Systems, Inc. (SASI) by John Swanson (and eventually renamed), Ansys serves the CAE (Computer Aided Engineering)/multiphysics engineering simulation market. Read more…

DoD Takes a Long View of Quantum Computing

December 19, 2023

Given the large sums tied to expensive weapon systems – think $100-million-plus per F-35 fighter – it’s easy to forget the U.S. Department of Defense is a Read more…

Intel’s Server and PC Chip Development Will Blur After 2025

January 15, 2024

Intel's dealing with much more than chip rivals breathing down its neck; it is simultaneously integrating a bevy of new technologies such as chiplets, artificia Read more…

Choosing the Right GPU for LLM Inference and Training

December 11, 2023

Accelerating the training and inference processes of deep learning models is crucial for unleashing their true potential and NVIDIA GPUs have emerged as a game- Read more…

Baidu Exits Quantum, Closely Following Alibaba’s Earlier Move

January 5, 2024

Reuters reported this week that Baidu, China’s giant e-commerce and services provider, is exiting the quantum computing development arena. Reuters reported � Read more…

Comparing NVIDIA A100 and NVIDIA L40S: Which GPU is Ideal for AI and Graphics-Intensive Workloads?

October 30, 2023

With long lead times for the NVIDIA H100 and A100 GPUs, many organizations are looking at the new NVIDIA L40S GPU, which it’s a new GPU optimized for AI and g Read more…

Shutterstock 1179408610

Google Addresses the Mysteries of Its Hypercomputer 

December 28, 2023

When Google launched its Hypercomputer earlier this month (December 2023), the first reaction was, "Say what?" It turns out that the Hypercomputer is Google's t Read more…

Leading Solution Providers

Contributors

AMD MI3000A

How AMD May Get Across the CUDA Moat

October 5, 2023

When discussing GenAI, the term "GPU" almost always enters the conversation and the topic often moves toward performance and access. Interestingly, the word "GPU" is assumed to mean "Nvidia" products. (As an aside, the popular Nvidia hardware used in GenAI are not technically... Read more…

Shutterstock 1606064203

Meta’s Zuckerberg Puts Its AI Future in the Hands of 600,000 GPUs

January 25, 2024

In under two minutes, Meta's CEO, Mark Zuckerberg, laid out the company's AI plans, which included a plan to build an artificial intelligence system with the eq Read more…

China Is All In on a RISC-V Future

January 8, 2024

The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The report, entitled "E Read more…

Shutterstock 1285747942

AMD’s Horsepower-packed MI300X GPU Beats Nvidia’s Upcoming H200

December 7, 2023

AMD and Nvidia are locked in an AI performance battle – much like the gaming GPU performance clash the companies have waged for decades. AMD has claimed it Read more…

Nvidia’s New Blackwell GPU Can Train AI Models with Trillions of Parameters

March 18, 2024

Nvidia's latest and fastest GPU, codenamed Blackwell, is here and will underpin the company's AI plans this year. The chip offers performance improvements from Read more…

Eyes on the Quantum Prize – D-Wave Says its Time is Now

January 30, 2024

Early quantum computing pioneer D-Wave again asserted – that at least for D-Wave – the commercial quantum era has begun. Speaking at its first in-person Ana Read more…

GenAI Having Major Impact on Data Culture, Survey Says

February 21, 2024

While 2023 was the year of GenAI, the adoption rates for GenAI did not match expectations. Most organizations are continuing to invest in GenAI but are yet to Read more…

Intel’s Xeon General Manager Talks about Server Chips 

January 2, 2024

Intel is talking data-center growth and is done digging graves for its dead enterprise products, including GPUs, storage, and networking products, which fell to Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire