IBM is making a big play in hybrid computing, seeking to marry its POWER8 processors with various kinds of accelerators and high-speed networking and opening up its chip and system software through the OpenPOWER Foundation. At the Open Innovation Summit in San Francisco today, IBM and its foundation partners talked about how their collaboration would deliver machines better tuned for hyperscale Web applications and data analytics, but the same technologies will no doubt also be deployed in traditional supercomputing environments.

One could argue that what IBM is trying to accomplish with the OpenPOWER Foundation in an open way with many partners up and down the hardware and software stacks is based on ideas it put to the test many years ago in the “Roadrunner” petascale-class x86-Cell hybrid system at Los Alamos National Laboratory. This was the first large-scale accelerated system, and IBM seeks to make what was exotic with Roadrunner six years ago easier to do today and something more akin to normal in the years ahead.

The POWER8 chip that was previewed today is about more than just increasing the core count by 50 percent and boosting the performance per socket on the order of 2X to 2.5X for various workloads compared to the POWER7 processors. IBM wants for all manner of accelerators to link very tightly with POWER8 processors and for scale-out clusters based on these chips to have the right kind of acceleration – be it a GPU, an FPGA, a DSP, or some other component – necessary for their particular jobs.

“The way I like to think about it is that with the POWER8 processor, we have created a superlane highway, and now we need cars driving on it,” explained Doug Balog, general manager of IBM’s Power Systems division, at the summit when announcing the new POWER8-based systems from IBM. “Very fast, very efficient vehicles. It is about that open interface that allows for that accelerator to attach to the POWER system.”

One of the interfaces that will be available to link accelerators to the POWER8 processors is IBM’s own Coherent Accelerator Processor Interface, or CAPI for short. This is an overlay on top of the PCI-Express 3.0 controllers on the POWER8 chip that will allow for high-speed linking between the CPU and accelerators and, more importantly, present a shared virtual memory space to applications across the memory attached to the CPU and any memory attached to the accelerator. Moving data back and forth between the CPU memory and the accelerator memory is a big hindrance to performance on accelerated machines, so making all memory addressable to all compute components is important.

Separately from IBM’s CAPI effort, but aligning nicely with it, NVIDIA has come up with its own NVLink interconnect, which will be used to hook its Tesla GPUs to POWER8 (and perhaps other) processors as well as to each other. Sumit Gupta, general manager of Tesla GPU Accelerated Computing Business unit at NVIDIA, said that NVLink would be incorporated into a future POWER processor design from IBM, and reminded everyone that the interconnect was part of the “Pascal” generation of GPUs from NVIDIA due in 2016 or so. NVIDIA is also going to license the technology behind NVLink to members of the OpenPOWER Foundation, Gupta said, and added that the two companies were in the meantime working on accelerating applications that combine POWER and Tesla compute. In the fourth quarter of this year, Gupta said, NVIDIA will deliver full support of its CUDA development environment for CPU-GPU hybrids on POWER processors, and in fact, IBM will also start shipping POWER8 systems that include Tesla GPU coprocessors.

“At the end of the day, the system is only as good as the software that takes advantage of it,” Gupta explained, “and that is why the future and the long-term focus is going to be around software.”

IBM is working with FPGA makers Xilinx and Altera to show the benefits of a hybrid setup running over the CAPI interface, so this is not just about GPU acceleration. Next week at the Impact2014 event, IBM and Xilinx will show a Memcached key value store application being accelerated by FPGAs and showing a factor of 35X better performance and an order of magnitude lower latency. A Monte Carlo simulation running on POWER machines accelerated by Altera FPGAs will show a factor of 200X speedup. Network adapter and switch maker Mellanox Technologies is also working with IBM to show how using Remote Direct Memory Access (RDMA) with a different key value store application boosted throughput and cut latencies by a factor of 10X.

There are a number of other benefits that come with POWER8 chips aside from high-speed links between processors and accelerators. The chips have a native little endian memory storage and accessing method, which is what x86 processors have and which stands in contrast to big endian ordering in memory. The important thing is this: with both x86 and POWER8 supporting little endian memory, applications that are coded from x86 systems to POWER8 systems are “a recompilation, a test, and a go,” as Balog put it. This is particularly important for C, C++, and Fortran and obviously has no bearing on interpreted languages like Java.

While the OpenPOWER Foundation members have not explicitly said they are seeking to accelerate traditional HPC applications, it is clear that these are core technologies that have been used – often first – in HPC systems. And there is no reason to believe that if IBM and its friends, including search engine giant Google, come up with more efficient ways of running plain vanilla POWER systems as well as hybrid machines that mix and match POWER chips and accelerators that these scale out systems will not end up in government and academic HPC centers. It will, as always, come down to having machines that suit a particular workload and at the right price. Suffice it to say that if IBM and its OpenPOWER Foundation partners can make a server that is low-cost enough to appeal to hyperscale datacenter operators, this will no doubt pique the interest of HPC centers.

In the meantime, IBM has divulged some details of the five new machines that it will sell based on the POWER8 processors. These are called the POWER Systems S-Class, and the “S” stands for scale out. Given the overwhelming adoption of Linux by the HPC community, the two Linux-only machines in the new line are probably the most appropriate, but one box that has slightly faster clock speeds might be interesting to HPC customers depending on what IBM charges for them.

The POWER S822L is a two-socket machine that fits into a 2U chassis, and it is probably the one that HPC shops will look at first. The system has room for two processor cards, which plug into the system board, and each one of them has a maximum of 512 GB of main memory. Customers can choose a POWER8 processor with ten of its twelve cores activated and running at 3.42 GHz or one with all twelve cores activated but running at only 3.02 GHz. This machine does not support cheap SATA disks, but does have room for a dozen 2.5-inch SAS drives or SSDs. It also has a storage cage with room for six 1.8-inch SSDs and has nine PCI-Express 3.0 slots. This machine will be available on June 10, and it supports Red Hat Enterprise Linux 6.5, SUSE Linux Enterprise Server 11 SP3, and Canonical Ubuntu Server 14.04 LTS. It can also run the POWERKVM hypervisor, a variant of the KVM hypervisor that IBM has created in conjunction with Red Hat and Canonical.

The POWER S812L comes with the same 2U chassis but only has one processor in it (the same options as the two-socket machine above) and only has six PCI-Express 3.0 peripheral slots. This machine will not ship until August, and will probably be less appealing to HPC shops because of its lower compute density compared to the POWER S822L.

The third machine that might see some HPC play is the POWER S822, which can run IBM’s AIX 6.1 or 7.1 operating systems or RHEL 6.5 or SLES 11 SP3. (It has not been certified to run Ubuntu Server, however.) This server can have one or two processor cards, and customers can choose between two different processors: a six-core POWER8 humming along at 3.89 GHz and a ten-core variant spinning at 3.42 GHz. Each socket in this machine supports up to 512 GB of memory, and it has six PCI slots with one processor card and nine with two processor cards.

IBM said that a base POWER Systems S-Class server would cost $7,973, but did not say what configuration or what specific system that cost was tied to. Big Blue is expected to put out pricing information on the new S-Class systems next week.