Sponsored by Intel
April 29, 2014

Emerging System Sets Stage for Exascale Science

Nicole Hemsoth

Today we welcome a new large-scale system into the high performance computing fold with the formal announcement of Cori, a new supercomputer set to be installed at NERSC in the mid-2016 timeframe. Known in its RFP stages as NERSC-8, the new machine will sport over 9,300 nodes, featuring the next-generation Knights Landing architecture housed within a Cray XC environment.

In the original request for vendor input on the system, NERSC said they required a new HPC environment to support the broad array of scientific projects that run at the center. This system had to “provide a significant upgrade in computational capabilities, with at least a ten-times increase in sustained performance over the NERSC-6 Hopper system on a set of representative benchmarks.” With 3 teraflops of double-precision peak performance per node expected from the Knight’s Landing-based Cray Cori machine, there is set to be a clear 10x (or more) improvement. The addition of over 400 GbS of IO bandwidth and 28 petabytes of disk make this quite a powerhouse—but again, the real emphasis is not on peak or capability, it’s on true application performance and showing a path to using new architectures and approaches for next generation science.

What’s interesting about the new supercomputer is that it’s been designed as a proving ground of sorts for some of the key barriers on the exascale computing front, including resiliency, programming to exploit massive levels of parallelism, and support for data-intensive scientific computing applications in software, hardware, memory and storage systems. Key to exploring solutions around these barriers are the Knight’s Landing manycore, self-hosted architecture and more novel approaches to extending reliability and performance with flash memory. The point of the system, as NERSC folks we talked to leading up to the announcement repeated constantly, has been to serve the highly diverse workloads of over 5,000 users that will make use of the system…not to appeal to compute-based benchmarks like LINPACK, although that sentiment is not new these days.

While we have often heard variables on the eventual core count of the Knight’s Landing processors set to appear in this system, Katie Antypas, head of NERSC’s Services Department, said there will be “more than sixty cores” on each of the cards.  But as Antypas repeated several times during our conversation about Cori, the real appeal has a lot less to do with compute horsepower than it does real application requirements. The access to high-bandwidth on-package memory  with the next-generation Intel part is the real appeal, she noted. “This is critical for our workloads because we’ve found that most of our applications aren’t limited by compute—they’re held back because of memory bandwidth.” While performance and efficiency are key, “for users, having this self-hosted architecture means there is no need to worry about moving data on and off a coprocessor.”

Antypas notes that even with a familiar programming environment and lessened emphasis on the challenges of data movement inside the node, there’s still a big optimization challenge ahead. “We know it will be a challenge for some of our users since they will need to find more parallelism in order to port their applications to a new architecture.” Still, she says, “we knew that for the long term to satisfy our mission to deliver more computing capability for our users, we needed to go down the manycore and more efficient route.”

There’s another unique element that the team will watch play out in advance of the wave of exascale systems eventually. The contract noted an option for burst buffer technology. In essence, this a layer of NVRAM that sits between the memory and disk to accelerate IO in the system. This is a core part of what Nick Wright, Advanced Technologies Group lead at NERSC will be watching once it’s up and running, both in terms of how it’s able to sate some key reliability concerns and to explore how it can enhance the increasingly important IOPS capabilities of the machine.

Wright says his team is looking at the burst buffer option for data-intensive computing as well as for addressing traditional HPC resiliency because of its checkpoint restart capabilities. “For data-intensive applications, one of the things about flash memory is that it has significantly higher IOPS than regular spinning disk—we’re seeing that many of the data-intensive apps are IOPS bound as well as general IO bandwidth bound, so we want to explore what new capabilities in scientific computing we can enable.”

For this piece of the system, Cray will be working with the software side but they’re still evaluating who the vendor will be for the hardware piece of the burst buffer. Wright says they want to integrate as much commodity technology as possible, but there’s benefit in waiting. The machine isn’t due for delivery for a while so that lets them ride out the drop in flash prices for a bit until they’re actually ready to pounce, instead of investing now in technology they’re not ready to use yet.

As Antypas said, “flash delivers bandwidth more cost effectively, so to give users the bandwidth they need, folks like us at NERSC have been buying really large parallel file systems. But the price of flash has come to the point that it looks much more promising for our supers. It can be a significant increase in bandwidth, and accelerating IO and spending more time computing is right what we want to do.”

Antypas and Wright agree that the burst buffer, both as a checkpoint and restarting merchanism to make rollbacks and checkpointing far faster and more efficient, as well as for driving data-intensive science, is something that they expect to see in exascale systems. They hope to share lessons learned for future systems—but for now are focusing on evolving applications according to the manycore architecture at hand, which represents a good view of the future.

As Sudip Dosanjh, Director of the National Energy Research Scientific Computing Center at Lawrence Berkeley National Laboratory summarized, “Cori will provide a significant increase in capability for our users and will provide a platform for transitioning our very broad user community to many core architectures. We will collaborate with Cray to ensure that Cori meets the computational and data needs of DOE’s science community.”

“We are thrilled to work with Cray in bringing the next generation of highly parallel supercomputers to market based on the Intel Xeon Phi processor – codenamed Knights Landing,” said Charles Wuischpard, Intel’s Vice President, Data Center Group and General Manager, Workstation and High Performance Computing. “Working closely with Cray, we will deploy the Many Integrated Core (MIC) architecture on the next generation Cray XC supercomputer, delivering over 3 teraflops of performance per single socket node to power a wide set of applications and taking an important and viable step towards Exascale.”

For some notable reads, check out the benchmarks here—congrats to our friends at NERSC and their new addition!