Charming Exascale Power Problems

By Osman Sarood, Laxmikant Kale & Esteban Meneses

July 30, 2014

Power, energy and reliability present major challenges to HPC researchers in their endeavor to build larger machines. As we approach the exascale era, both hardware and software designers need to account for these challenges while optimizing performance. The Parallel Programming Laboratory (PPL) at the University of Illinois at Urbana-Champaign (UIUC) has been actively working on meeting these challenges by leveraging the adaptive runtime system of the Charm++ programming model.

Current petascale machines have Mean Time Between Failures (MTBF) that can be anywhere from a few hours to days. Some reports predict exascale machines will have an MTBF in the range of 35-40 minutes. Intriguingly, past research describes a relation between a processor’s temperature and its reliability: failure rates double with every 10C increase in temperature. Our work applies this relationship between processor temperature and reliability by restraining processor temperature, thereby reducing the frequency of faults and consequently improving application performance in fault-prone environments.

There are costs and benefits to improving reliability through temperature control driven by Dynamic Voltage and Frequency Scaling (DVFS). Improved reliability helps not only by directly decreasing failures; it also allows the code to checkpoint less frequently, decreasing overhead. However, it comes at a cost of slower processors and increased load imbalance.

By restraining processor temperatures, we can empower the runtime system to set the expected failure rate of the system, adjusting it within a feasible range. Our control strategy lets each processor work at its maximum frequency as long as its temperature is below a threshold parameter. If a processor’s temperature crosses the maximum threshold, it is controlled by decreasing the voltage and frequency using DVFS. When the voltage and frequency are reduced, its power consumption will drop and hence the processor’s temperature will fall.

When DVFS adjusts frequencies differently across the cores in a cluster, the workloads on those cores change relative to one another. This can significantly degrade performance of a tightly coupled parallel application, where processors synchronize after a time step before proceeding to the next time step. We mitigate the resultant timing penalty with a load balancing strategy that is conscious of the difference in speeds for different processors.

Our load balancing strategy, based on overdecomposition and object migration, uses the Charm++ adaptive runtime system to increase processor utilization. It analyzes the current load of each processor according to its new frequency and determines if it is overloaded or under-loaded. Once this decision is made, our scheme intelligently exchanges objects from overloaded (hot) processors to under-loaded (cold) processors to balance load. Temperature checking and corresponding load balancing can be invoked at user defined intervals.

One twist in this work is that different applications vary both in how hot they will make processors at a given frequency, and in how their performance is affected by different frequencies. Note that this implies different applications may actually experience a different MTBF on the same machine! Thus, we use three applications that present different conditions.

To gauge the effects of temperature control on MTBF and hence application performance, we formulate a model that relates total execution time of an application to reliability and the associated slowdown for temperature restraint. The model accounts for different execution speed at different frequencies, checkpointing overhead and recovery time depending on MTBF, and the additional overhead of experiencing and adapting to load imbalance. We validate the accuracy of our model for each application using a small experimental testbed.

We use our validated model to project the benefits of our scheme for larger machines. Our results point towards a tradeoff between improvement in reliability and the associated cost of applying temperature control. This tradeoff determines the optimal temperature threshold for a given application and machine size.

The following figure compares the machine efficiency (proportion of time spent doing useful work) for a 2D stencil application between a baseline run without temperature control and a constrained run with the temperature threshold set to 48C. Below 32K sockets, we get a lower efficiency than the baseline. However, above 32K sockets, our scheme starts outperforming the baseline case. For reference, the Blue Waters system at NCSA has nearly 50K sockets. For 256K sockets, our scheme is projected to operate the machine with an efficiency of 0.29 compared to 0.08 for the baseline. Finally, for 340K sockets, the baseline efficiency drops to 0.01, making the machine almost nonoperational, whereas our scheme can still operate the machine at an efficiency of 0.22.

exascale_race

These promising results encourage us to extend our work by investigating more detailed models, larger experimental systems, and more advanced fault tolerance protocols, such as message logging and parallel recovery.

This work is part of a research theme in our group: using adaptive runtime control to deal with the challenges presented by sophisticated applications and complexities of hardware. The Parallel Programming Laboratory has developed Charm++ for the past 20 years as a production quality parallel programming language, used in many CSE applications, including the Gordon Bell-winning biomolecular simulation program NAMD.

Author Biography:

Osman Sarood is a final year PhD student in the UIUC Computer Science department. His research is focused on performance optimization under thermal and power constraints.

Esteban Meneses is a Research Assistant Professor working in the Center for Simulation and Modeling at the University of Pittsburgh. His research is focused on load balancing and fault tolerance techniques for large-scale parallel applications. He holds a PhD degree in Computer Science from UIUC.

Laxmikant Kale received his PhD in computer science from State University of New York, Stony Brook, in 1985. He joined the Computer Science faculty of UIUC as an Assistant Professor in 1985, where he is currently employed as a full Professor. His research spans parallel computing, including parallel programming abstractions, scalability, automatic load balancing, communication optimizations, and fault tolerance. He has collaboratively developed several scalable CSE applications.

Subscribe to HPCwire's Weekly Update!

Be the most informed person in the room! Stay ahead of the tech trends with industry updates delivered to you every week!

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing power it brings to artificial intelligence.  Nvidia's DGX Read more…

Call for Participation in Workshop on Potential NSF CISE Quantum Initiative

March 26, 2024

Editor’s Note: Next month there will be a workshop to discuss what a quantum initiative led by NSF’s Computer, Information Science and Engineering (CISE) directorate could entail. The details are posted below in a Ca Read more…

Waseda U. Researchers Reports New Quantum Algorithm for Speeding Optimization

March 25, 2024

Optimization problems cover a wide range of applications and are often cited as good candidates for quantum computing. However, the execution time for constrained combinatorial optimization applications on quantum device Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at the network layer threatens to make bigger and brawnier pro Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HBM3E memory as well as the the ability to train 1 trillion pa Read more…

Nvidia Appoints Andy Grant as EMEA Director of Supercomputing, Higher Education, and AI

March 22, 2024

Nvidia recently appointed Andy Grant as Director, Supercomputing, Higher Education, and AI for Europe, the Middle East, and Africa (EMEA). With over 25 years of high-performance computing (HPC) experience, Grant brings a Read more…

Q&A with Nvidia’s Chief of DGX Systems on the DGX-GB200 Rack-scale System

March 27, 2024

Pictures of Nvidia's new flagship mega-server, the DGX GB200, on the GTC show floor got favorable reactions on social media for the sheer amount of computing po Read more…

NVLink: Faster Interconnects and Switches to Help Relieve Data Bottlenecks

March 25, 2024

Nvidia’s new Blackwell architecture may have stolen the show this week at the GPU Technology Conference in San Jose, California. But an emerging bottleneck at Read more…

Who is David Blackwell?

March 22, 2024

During GTC24, co-founder and president of NVIDIA Jensen Huang unveiled the Blackwell GPU. This GPU itself is heavily optimized for AI work, boasting 192GB of HB Read more…

Nvidia Looks to Accelerate GenAI Adoption with NIM

March 19, 2024

Today at the GPU Technology Conference, Nvidia launched a new offering aimed at helping customers quickly deploy their generative AI applications in a secure, s Read more…

The Generative AI Future Is Now, Nvidia’s Huang Says

March 19, 2024

We are in the early days of a transformative shift in how business gets done thanks to the advent of generative AI, according to Nvidia CEO and cofounder Jensen Read more…

Nvidia’s New Blackwell GPU Can Train AI Models with Trillions of Parameters

March 18, 2024

Nvidia's latest and fastest GPU, codenamed Blackwell, is here and will underpin the company's AI plans this year. The chip offers performance improvements from Read more…

Nvidia Showcases Quantum Cloud, Expanding Quantum Portfolio at GTC24

March 18, 2024

Nvidia’s barrage of quantum news at GTC24 this week includes new products, signature collaborations, and a new Nvidia Quantum Cloud for quantum developers. Wh Read more…

Houston We Have a Solution: Addressing the HPC and Tech Talent Gap

March 15, 2024

Generations of Houstonian teachers, counselors, and parents have either worked in the aerospace industry or know people who do - the prospect of entering the fi Read more…

Alibaba Shuts Down its Quantum Computing Effort

November 30, 2023

In case you missed it, China’s e-commerce giant Alibaba has shut down its quantum computing research effort. It’s not entirely clear what drove the change. Read more…

Nvidia H100: Are 550,000 GPUs Enough for This Year?

August 17, 2023

The GPU Squeeze continues to place a premium on Nvidia H100 GPUs. In a recent Financial Times article, Nvidia reports that it expects to ship 550,000 of its lat Read more…

Shutterstock 1285747942

AMD’s Horsepower-packed MI300X GPU Beats Nvidia’s Upcoming H200

December 7, 2023

AMD and Nvidia are locked in an AI performance battle – much like the gaming GPU performance clash the companies have waged for decades. AMD has claimed it Read more…

DoD Takes a Long View of Quantum Computing

December 19, 2023

Given the large sums tied to expensive weapon systems – think $100-million-plus per F-35 fighter – it’s easy to forget the U.S. Department of Defense is a Read more…

Synopsys Eats Ansys: Does HPC Get Indigestion?

February 8, 2024

Recently, it was announced that Synopsys is buying HPC tool developer Ansys. Started in Pittsburgh, Pa., in 1970 as Swanson Analysis Systems, Inc. (SASI) by John Swanson (and eventually renamed), Ansys serves the CAE (Computer Aided Engineering)/multiphysics engineering simulation market. Read more…

Choosing the Right GPU for LLM Inference and Training

December 11, 2023

Accelerating the training and inference processes of deep learning models is crucial for unleashing their true potential and NVIDIA GPUs have emerged as a game- Read more…

Intel’s Server and PC Chip Development Will Blur After 2025

January 15, 2024

Intel's dealing with much more than chip rivals breathing down its neck; it is simultaneously integrating a bevy of new technologies such as chiplets, artificia Read more…

Baidu Exits Quantum, Closely Following Alibaba’s Earlier Move

January 5, 2024

Reuters reported this week that Baidu, China’s giant e-commerce and services provider, is exiting the quantum computing development arena. Reuters reported � Read more…

Leading Solution Providers

Contributors

Comparing NVIDIA A100 and NVIDIA L40S: Which GPU is Ideal for AI and Graphics-Intensive Workloads?

October 30, 2023

With long lead times for the NVIDIA H100 and A100 GPUs, many organizations are looking at the new NVIDIA L40S GPU, which it’s a new GPU optimized for AI and g Read more…

Shutterstock 1179408610

Google Addresses the Mysteries of Its Hypercomputer 

December 28, 2023

When Google launched its Hypercomputer earlier this month (December 2023), the first reaction was, "Say what?" It turns out that the Hypercomputer is Google's t Read more…

AMD MI3000A

How AMD May Get Across the CUDA Moat

October 5, 2023

When discussing GenAI, the term "GPU" almost always enters the conversation and the topic often moves toward performance and access. Interestingly, the word "GPU" is assumed to mean "Nvidia" products. (As an aside, the popular Nvidia hardware used in GenAI are not technically... Read more…

Shutterstock 1606064203

Meta’s Zuckerberg Puts Its AI Future in the Hands of 600,000 GPUs

January 25, 2024

In under two minutes, Meta's CEO, Mark Zuckerberg, laid out the company's AI plans, which included a plan to build an artificial intelligence system with the eq Read more…

Google Introduces ‘Hypercomputer’ to Its AI Infrastructure

December 11, 2023

Google ran out of monikers to describe its new AI system released on December 7. Supercomputer perhaps wasn't an apt description, so it settled on Hypercomputer Read more…

China Is All In on a RISC-V Future

January 8, 2024

The state of RISC-V in China was discussed in a recent report released by the Jamestown Foundation, a Washington, D.C.-based think tank. The report, entitled "E Read more…

Intel Won’t Have a Xeon Max Chip with New Emerald Rapids CPU

December 14, 2023

As expected, Intel officially announced its 5th generation Xeon server chips codenamed Emerald Rapids at an event in New York City, where the focus was really o Read more…

IBM Quantum Summit: Two New QPUs, Upgraded Qiskit, 10-year Roadmap and More

December 4, 2023

IBM kicks off its annual Quantum Summit today and will announce a broad range of advances including its much-anticipated 1121-qubit Condor QPU, a smaller 133-qu Read more…

  • arrow
  • Click Here for More Headlines
  • arrow
HPCwire