“This market, this industry, is poised for a fairly fundamental transformation,” Raj Hazra, Vice President and General Manager of Intel’s High Performance Computing division, told a group at the company’s SC14 briefing on their future investments in HPC.
The comment came as a counterpoint to the lack of news around stunning changes in the Top 500 list of supercomputers as well as the general sentiment at the show that HPC momentum had suddenly ground to a halt. While many recognize that this is a temporary standstill, including Hazra, who is seeing the industry on track to upend the current performance, efficiency, and code trends, the insight from the top chipmaker about what the future holds was welcome.
While many already may be aware that Intel finally let loose on some details around the upcoming Knights Landing chips, which are due in 2015 and are already set to be outfitted on large-scale supercomputers including Trinity, Cori, and the newly announced KAUST machines, it’s worth asking why these revelations are being made at this early stage. This is even more of a wonder following their SC14 news of a the next-next generation Xeon Phi, codenamed Knights Hill.
“We’re making a sustained, multi-generational investment in the Xeon Phi family,” said Charles Wuischpard, General Manager of Workstations and HPC at Intel. “A lot of that has to do with the fact that we have customers like one who told us that they’ve put half a billion dollars into each of six codes over the last twenty years and are now planning to support manycore architectures with the Knights family. That’s a big responsibility and we want to make it clear this isn’t a one-shot deal.”
Wuischpard made it clear that it’s essential for their customers to see clearly that the Knights family will be bestowed with many years of investment. “We’re showing adoption and readiness for Knight’s Landing,” he explained. “So far over 50 system providers are signed up building boards and chassis to incorporate it and we have over 100 petaflops of customer commitment and more in the wings waiting on future procurements.” He also noted that while most have been thinking of it as a socketed part (which will be binary compatible with current Xeons) there are use cases on the horizon that might benefit from having a card—something that will be around the corner at a different time than the official release.
While Intel still hasn’t dished on exactly how many cores will appear on the Knights Landing chips, stating only that there will be more than 60, it was revealed earlier in the week that the OmniPath fabric (formerly known as OmniScale) will be integrated on the 14 nanometer part. The expectation is that it will hit 3 teraflops of peak double-precision capability. This is matched with the news we carried earlier last year about Intel’s work with Micron to bring the Hybrid Memory Cube on board, pushing it close to the processor in a much smaller space than current generation Xeon Phis.
There is very little available about Knights Hill and how soon it will follow on the heels of Knights Landing, it is expected to follow a 10 nanometer trajectory, although Wuischpard says that there are various elements, not the least of which are the memory and interconnect pieces, that will determine the specs for the future architecture. So far, other than the code name (and some great speculation here) this is what we’re left to work with. For Intel, however, it doesn’t seem to be critical at this time to share details, but rather to show that as per usual, well before a new product rolls out to general availability, there are already teams at work developing its next generation. This takes us back to Wuishpard’s point about showing high-value customers that all of their investments in code and future manycore architectures is placed well with Intel.
The critical part of these efforts will be on the code modernization and development front, which has been a sustained focus for Intel with its on-site work with customers who have custom proprietary codes, to large national labs and academic centers, including NERSC, which will need to get its codes primed for the eventual Knights Landing-based machine coming their way.
According to Hazra and his colleague, Charles Wuishpard, it’s time to stop thinking of Intel in its chip box and recognize how they’re taking a platform approach to the entire system. From their current investments at the Lustre, Omni Path fabric, and code modernization levels all the way up the systems chain, the pair were adamant that Intel is set to take a lead through continued integration and codesign in both hardware and software.
“In HPC we’re not just a chip company,” said Hazra. “If the data is computed on, if it’s being moved, if it’s being stored, we’re engaged in it. This isn’t just a business aspiration or model—it’s the way scalable systems have to be designed… For balanced systems that are highly optimized and workload targeted, they must be designed at the system level and have interplay between the parts.”
“We are looking at systems at multiple scales and looking for more efficient compute, more programmable efficient compute, and ease of deployment,” noted Hazra. Of their current Knights family, he says while they’ve shared what is new in the roadmap generally, Intel’s strategies are set and now they’re executing along those lines with the expectations of feeding the ecosystems around the many layers of the next generation of HPC systems. “We’re excited about having made some bets in the manycore space a couple of years ago that’s starting to pay off. It’s a steady continuance of building and engagement to get the ecosystem up and running.”