There’s a growing interest among silicon providers backing RISC-V to introduce 48-bit computing in custom chips to meet their specific requirements.

The 48-bit long instructions focus is more as a middle ground between 32-bit and 64-bit, which has largely been the focus of chips and instruction sets until now.

“RISC-V is not pushing any 48-bit instructions right now. But there are some members who are doing custom instructions that are 48-bit… and it is mostly driven by immediate values,” said Mark Himelstein, chief technology officer at RISC-V International.

RISC-V is an open-source instruction set architecture that companies can license for free and then modify to their own needs.

The RISC-V design is modular, meaning that companies can add or subtract modules depending on their requirements. The instruction set is a common tissue on which compute cores – which could be for graphics, artificial intelligence, vector cryptography, etc. – can be linked.

SiFive has developed its own RISC-V processor called the P650 which it has compared to Arm’s Cortex-77 chip. Intel is also working with Barcelona Supercomputing Centre to develop a RISC-V high-performance chip, and is investing billions to make chips based on all major architectures including RISC-V.

The RISC-V architecture is popular in controllers and embedded applications, which are largely 16-bit and 32-bit. Himelstein said that 48-bit instructions may be gathering steam in embedded computing. He added there also conversations on 128-bit instructions in the RISC-V community.

Companies had to rely on getting instruction sets from the big vendors every few years, and either needed a lot of money or influence to get customized chips. RISC-V cuts that reliance and provides a free framework so companies build chips to meet their own computing needs, Himelstein said.

“When you want to add some big prime number or something to a register, that’s harder, because you’ve run out of bits and places to put them. The people who are doing 48-bit have a very large immediate field. The reason they want to do that is their only other choice is to load that value from memory into a register and then add it. If they have it as part of the instruction stream, they don’t have to do that. And in certain workloads, that’s a benefit,” Himelstein said.

The focus on 48-bit instructions is to move up from 32-bit, but not get to 64-bit, chip experts said.

The jump to 48-bits long instructions would make sense if someone wanted more encoding space, and adding new instructions could be helpful, said David Kanter, an analyst at Real World Technologies.

A main value proposition of RISC-V are those custom instructions.

“I’m guessing the community just ran out of room and needs more,” Kanter said.

The 48-bit instructions are non-standard, and they have an opcode format that has a big immediate.

“The same way today we allow the mingling of 16-bit and 32-bit instructions, they allow the mingling of 16-bit, 32-bit and 48-bit instructions. It’s in the normal instruction stream,” Himelstein said.

RISC-V is trying to build a simple and elegant modular design, and also trying to reduce fragmentation with input from the community. The goal is not to repeat the mistakes from the past.

“MIPS started as simple and elegant and became pretty complex. You had lots of various features in various chips that people tried out over the years that they thought were good or bad, and those have gone by the wayside,” Himelstein said.

RISC-V is down to a standard set of registers which is simple and flat, Himelstein said, adding “we get to sort of stand on the shoulders of giants and learn from their lessons.”

Himelstein wasn’t sure of the applications that RISC-V members would use for 48-bit instructions. Kevin Krewell, an analyst at Tirias Research, wasn’t sure either, but said it could be for storage.

“Some workloads need more than 32 bits, but don’t want to use floating point math because of the extra power and silicon. The other reason could be a very large address space is needed for extremely large data storage,” Krewell said.

Someone would have to want to run memory management in software, Krewell said, adding that “applications processors have dedicated memory management unit (MMU) hardware to manage memory pages. Having a 48-bit data path would allow software to manage large memory arrays without an MMU.”