HPCwire: The x86 Dynasty

The Leading Source for Global News and Information Covering the Ecosystem of High Productivity Computing

Leading HPC
Solution Providers

HPCwire >> Blogs

Blog: From the Editor

From the Editor | Main Blog Index

January 05, 2007

The x86 Dynasty

The longevity of the x86 architecture is perhaps one of the most surprising achievements of the Information Age thus far. Nobody, probably not even its Intel inventors, envisioned the dominance it has attained in the industry. After more than 25 years, the lowly x86 rules the all-important desktop, laptop and server markets.

For the past decade the x86 has been swallowing the high performance computing market, paralleling the rise of cluster computing. In the enterprise market, RISC/Unix boxes have been giving way to x86/Linux machines. And finally, with last year's conversion of Apple from PowerPC to Intel, the last bastion of non-x86 personal computers was removed from the desktop. In fact, had IBM anticipated the critical importance of desktop platform earlier and been a little quicker on the trigger with the development of the PowerPC chip, the whole history of computing might have followed a very different path.

As it was, the "Wintel" platform attracted a substantial software base in the 1980s before any RISC competitors could mount a challenge. The early accumulation of software, especially compiler/runtime tools and system software, created the initial momentum which propelled the x86 forward. With the thousands of applications that now run on x86 platforms, the cost of losing binary compatibility would be overwhelming for many users. It represents the technological version of the rich-get-richer syndrome: The bigger your market share, the more developers will be attracted to your architecture, which results in yet more market share.

Which brings us to the question: Will the x86 architecture ever lose its dominance? And if so, how will this happen? In 2020 it's conceivable that we'll be using terascale processors (and exascale supercomputers) based on the x86 ISA and implemented on post-CMOS technology. The demise of the x86 has been predicted before, so I hesitate to write its epitaph here. But all technologies have a lifespan and there is reason to believe that the architecture might not survive the age of terascale processors.

One problem to confront is that we're running out of Moore's Law. Before non-silicon-based processor technology -- compound semiconductors, carbon nanotubes, nanowires, molecular electronics, three-dimensional transistor designs and spintronics -- is developed and commercialized, the physics of sub-32nm process technology will constrain the number of transistors that can be placed on a die. The general-purpose x86 architecture, with its relatively complex instruction set, has to drag around a lot of transistors and microcode that have only limited utility for many types of computing, including high performance computing.

There's reason to believe that some the problems of sub-32nm technology will actually be solved, but most analysts believe CMOS-based silicon devices will no longer be practical at some point between 2015 and 2020. When this happens, transistor space on the die will become such a limiting factor that more efficient processor architectures will have an enormous advantage.

But even before that occurs, Intel and AMD may have moved beyond their x86 heritage. The current limitations of power consumption and heat dissipation are causing chipmakers to not only explore multi-core designs, but alternative processing engines as well. While the engineers at Intel and AMD have been extremely clever at increasing performance/watt, the market demand seems to be outstripping their efforts.

With the acquisition of ATI, AMD seems to have its sights set on a hybrid CPU-GPU approach, which could theoretically evolve away from strict x86 compatibility. The addition of GPU cores to general-purpose processors may be part of a trend that portends greater processor heterogeneity -- the Cell chip being an early example. As for the x86-only roadmap, AMD has not publicized any plans beyond an 8-core processor. Of course, the company would be expected to change direction if their major customers demanded a many-core x86 solution.

Intel, itself, has actually tried to move beyond the x86 twice before (not counting the i432 processor), once with the i860/i960 chips and more recently with the Itanium processor. The failure of the i860 and the (as yet) unrealized potential of the Itanium shows how even Intel can be a victim of its own success. In 2006, the company previewed a very non-x86 80-core prototype of a terascale processor, which it expects to commercialize by the middle of the next decade. Intel will be showing the next prototype of this processor at the upcoming International Solid-State Circuits Conference next month in San Francisco. According to Intel, "the 65nm 100-million transistor die is designed to achieve a peak performance of 1.0 teraflops at 1V while dissipating 98 watts."

With its (Niagara) UltraSPARC T1 chip, Sun Microsystems has demonstrated that a simplified processor can achieve much greater throughput than a more general-purpose architecture. The TI processor provides up to eight 4-way multithreaded cores (32 threads), while consuming just 72 watts. The processor is low on floating-point horsepower, making it unsuitable for scientific computing, but the design is well suited for Web servers and a wide variety of enterprise applications.

In contrast, SiCortex, an HPC cluster startup, developed a non-x86 architecture expressly targeted for high performance technical computing. Its MIPS-based chip holds six 64-bit CPUs, cache, two interleaved memory controllers, the interconnect fabric links and switch, a DMA Engine, and a PCI Express interface. The simplicity of the MIPS architecture enables a tightly integrated solution and claims two orders of magnitude more performance/watt compared to a typical x86 system. Their 5.8-teraflop, 8-terabyte cluster is housed in a single cabinet and consumes just 20 kilowatts of power. The system relies on GNU and PathScale compilers for the MIPS target and open source Linux to insulate the applications from the non-standard hardware.

The SiCortex case is interesting in another respect. The MIPS CPU, like many RISC chips, was a high-end processor that got relegated to the embedded market when it couldn't compete as a workstation chip. The embedded market is much more diversified than the desktop, laptop and server markets. The latter community runs a relatively limited set of applications, while embedded applications are much more diverse and include devices such as PDAs, laser printers, set-top boxes, network switches, automobile diagnostic controllers, game machines, etc. The diversity is reflected in the diversity of processors: PowerPC, MIPS, ARM, 68K, SPARC, and even x86. Due to the dynamic nature of the market, no processor has maintained dominance for any length of time.

But as power, heat and space constraints become increasingly important in the non-embedded world, the simpler, embedded RISC processors are looking more attractive. The simpler processor architectures enable more aggressive multi-core and multi-threaded designs. This advantage is especially important for HPC applications, where parallel throughput is usually much more critical than single thread performance. IBM's use of the energy-efficient PowerPC processors in its Blue Gene supercomputers is a reflection of this strategy.

While the end of the x86 dynasty will not happen in 2007, some of the forces that could end its dominance are already in motion. In a decade or so we'll probably look back at this time and wonder how we could ever have been so dependent on a single architecture for so long. Its 30-year reign will be seen as an anomalous blip in the early history of computer technology.

-----

As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at editor@hpcwire.com.

Posted by Michael Feldman - January 5 @ 12:00AM

Discussion

There are 0 discussion items posted.

Join the Discussion

You must be a registered user in order to comment on HPCWire stories.

Members enjoy:

	Access to Special Content, including Podcasts, Webcasts, and Whitepapers and more!
	Ability to take an active role in the discussions that are shaping the HPC technology discipline!
	Special offers available only to HPCWire members!

Become a Registered User Today!

Registered Users Log in Here to Comment

Email Address:	Password (case sensitive)

Remember me	Forgot Password?

Michael Feldman

Michael Feldman is the editor of HPCwire.

More Michael Feldman

Feature Articles

'Coopetition' Helps the UK HPC Market Go 'Round

The size and diversity of the HPC market in the United States supports a varied set of system providers and integrators. But in Europe, and the United Kingdom in particular, the market has a different shape.
Read More...

The Week in Review

PRACE to evaluate petaflops prototypes; Acadamic roundtable discusses the computing industry's talent pool; and WRF benchmark data are released. John West recaps those stories and more in our weekly wrap-up.
Read More...

Semantic Supercomputing Reaps Competitive Advantage from Patent Data

Since the first patent was issued for a Venetian statue in 1471, 60 million patents have been awarded around the world, with four million patents actively in force today worldwide. And 800,000 new inventions are registered every year. While the data is public, current search tools are inconvenient and inadequate to the needs of professionals. Semantic supercomputing techniques are helping researchers tackle this difficult challenge.
Read More...

Read more HPCwire features...

Top Headlines

25 Years of Conventional Evaluation of Data Analysis Proves Worthless In Practice

Sep 05 | Uppsala University | Swedish researchers are revealing that "intelligent" computer-based methods for classifying patient samples is worthless when it comes to practical problems. Read more...

Three Dimensional Scans Could Revolutionise Brain Surgery

Sep 03 | Telegraph.co.uk | A new form of three dimensional scans could revolutionise brain surgery within a year, doctors claim. Read more...

Marching Penguins: Monitoring Your HPC Cluster

Sep 03 | Linux Magazine | In HPC, most attention is paid to utilization and performance, rather than service availability and problem notification. This article focuses on the latter Read more...

Big Data: Welcome to the Petacentre

Sep 03 | Nature News | What does it take to store bytes by the tens of thousands of trillions? Read more...

UD Scientist Finds Quicker Computer On-Ramp

Sep 01 | Delaware Online | In the world of supercomputer-powered science, speed is everything, and an open road can lead to the promised land. Read more...

Read more headlines...

Featured Whitepapers

SUSE® Linux Enterprise Server for High Performance Computing

Sep 05 | | The excellent scalability features of Linux, in addition to robust security and performance makes it an excellent choice for server systems, especially in the high performance computing area.

“Going Parallel - An Implementation Guide”

Sep 01 | | The paper outlines the basic steps and tools involved in the process of migrating a desktop application to a parallel environment.

Improving Performance and Manageability for Seismic Processing and Imaging Applications with Parallel Storage

Jun 05 | | As pressure increases on the upstream seismic processing community to deliver ever-higher levels of productivity and efficiency, a new generation of storage solutions will be required that allow the maximum utilisation of high-performance computing (HPC) Linux cluster resources, together with the minimum of management overhead.

View the White Paper Library

Multimedia

Video White Paper: Architecting a Better Network Storage Solution

BlueArc's Titan architecture represents an evolutionary step in file servers by creating a hardware-based file system that can scale bandwidth, IOPS, and overall data capacity well beyond conventional software-based devices. With its ability to virtualize a massive storage pool of up to four usable petabytes of tiered storage, Titan can scale with growing data requirements, offering a competitive advantage for businesses, researchers, or other enterprises seeking to better manage data growth while still ensuring optimal performance.

Podcast: Interview with Ben Bennett of ClearSpeed Technology

Today, HPC organizations are requiring substantially more floating point performance to solve real-world problems. In this podcast, Ben Bennett, ClearSpeed General Manager, discusses how acceleration technology can improve the overall performance of standard x86-based systems...