HPCwire: Anticipating the Fall: Application Performance Has Chased Multicore's Speed Right Over a Cliff

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June 05, 2008

Anticipating the Fall: Application Performance Has Chased Multicore's Speed Right Over a Cliff

Wile E. Coyote is doomed. Hanging in space, he is about to fall, and everyone knows it but him. We all saw it coming. Poor Coyote.

Yet strangely, he doesn't fall right away. According to the alternate-reality rules of cartoon physics, the Coyote must first look down and realize he is standing in thin air. He then has time to gather his thoughts, issue a final desperate wave, and then finally -- poof! -- he plummets body first, leaving his head in the frame for the viewers to witness a comical last-second grimace before that too disappears.

Know what else we saw coming? The crash in HPC application performance that is being brought about by the transition to multicore processors. We've been watching the race, as applications (Codus productivus) desperately chased processors (Waferii siliconium) up the performance mountain. Suddenly multicore came and -- meep! meep! -- the CPUs put on a burst of speed and zoomed around a bend, leaving application software headed for a cliff. HPC users were doomed. Everyone knew it. Poor users.

What's this? Application performance hasn't dramatically suffered? Users are satisfied with the performance they're getting? How is this possible? The answer: cartoon physics.

According to our most recent research, the reason performance hasn't plummeted is that users haven't been forced to deal with the problem yet. Rather than introducing a new level of parallelism at the socket level, most users have responded by running separate jobs on each core. Sure, they're buying a lot more memory to do that -- configured memory per core is staying relatively stable, and therefore configured memory per socket is skyrocketing -- but at least the application is scaling. For now.

We've gone off a cliff; we just don't know it yet. Because those cores aren't getting any faster, we're soon going to come to grips with the reality that new tools or programming models are needed in order to keep up the race. Look down, everybody. The ground isn't there. Now is the time to hold up a little "Oh, no!" sign and wave to the camera.

This is going to hurt, but fear not. The Coyote is resilient, and he always comes up with a new scheme. Soon he'll be back in the race and chasing right behind the Road Runner again.

The ISC conference in Dresden is coming up, and the new things I'll most want to see are tools for improving application performance yield in large-scale, multicore systems. Acme Application Optimizers, anyone?

Posted by Addison Snell - June 5 @ 8:38PM

Discussion

There are 3 discussion items posted.

Submitted by $user.username on 06/09/2008 - 6:33AM

Multicore poses fundamental challenges for industrial HPC, but what you're observing highlights the importance of real physics, not cartoon physics. I'm expected to deliver performance, but above all I have to insure the physical realism that 10 or more years of development put in the code.

Even Wile E. Coyote couldn't devise a way to make the software life cycle keep pace with hardware. What we can do is strategic action to be sure we're somewhere else by the time the falling anvil hits.

Post #1

Submitted by $user.username on 06/10/2008 - 9:09AM

Addison - good post and none too soon.

The current workaround your research describes isn't sustainable b/c the added memory per processor is eating into the all too constrained power/flop ratio.

Unfortunately, the harsh reality is that the applications themselves will have to get more efficient.

eeeeegaaads! not that perhaps we need to introduce mini the mooch into this cartoon special

Post #2

Submitted by tuccillo on 06/11/2008 - 9:43AM

While the clock speed of the cores may not be increasing (much) with the continued rise in the number of cores per chip, the availability of more cores can result in increased performance for parallel applications. Of course, if your favorite application isn't parallelized using a message passing or threads approach or it's scalability is extremely limited then you are out of luck. I would argue that there are a substantial amount of message passing codes that do exhibit good scalability and their problem sizes are only getting larger (which should allow for the application of more cores). Clearly the trend is for more available cores so the pressure is on to improve scalability of your code if you need increased performance. The upcoming Intel Nehalem should address the rather disturbing trend towards less memory bandwidth per core as the number of cores per chip has increased.

Post #3

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Addison Snell

Addison Snell is the Vice President and General Manager of Tabor Research, Inc.

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