The Leading Source for Global News and Information Covering the Ecosystem of High Productivity Computing
HPC Matters is a joint blog consisting of contributors from the Tabor Communications team on their observations and insights into HPC matters.
June 05, 2008
Wile E. Coyote is doomed. Hanging in space, he is about to fall, and everyone knows it but him. We all saw it coming. Poor Coyote.
Yet strangely, he doesn't fall right away. According to the alternate-reality rules of cartoon physics, the Coyote must first look down and realize he is standing in thin air. He then has time to gather his thoughts, issue a final desperate wave, and then finally -- poof! -- he plummets body first, leaving his head in the frame for the viewers to witness a comical last-second grimace before that too disappears.
Know what else we saw coming? The crash in HPC application performance that is being brought about by the transition to multicore processors. We've been watching the race, as applications (Codus productivus) desperately chased processors (Waferii siliconium) up the performance mountain. Suddenly multicore came and -- meep! meep! -- the CPUs put on a burst of speed and zoomed around a bend, leaving application software headed for a cliff. HPC users were doomed. Everyone knew it. Poor users.
What's this? Application performance hasn't dramatically suffered? Users are satisfied with the performance they're getting? How is this possible? The answer: cartoon physics.
According to our most recent research, the reason performance hasn't plummeted is that users haven't been forced to deal with the problem yet. Rather than introducing a new level of parallelism at the socket level, most users have responded by running separate jobs on each core. Sure, they're buying a lot more memory to do that -- configured memory per core is staying relatively stable, and therefore configured memory per socket is skyrocketing -- but at least the application is scaling. For now.
We've gone off a cliff; we just don't know it yet. Because those cores aren't getting any faster, we're soon going to come to grips with the reality that new tools or programming models are needed in order to keep up the race. Look down, everybody. The ground isn't there. Now is the time to hold up a little "Oh, no!" sign and wave to the camera.
This is going to hurt, but fear not. The Coyote is resilient, and he always comes up with a new scheme. Soon he'll be back in the race and chasing right behind the Road Runner again.
The ISC conference in Dresden is coming up, and the new things I'll most want to see are tools for improving application performance yield in large-scale, multicore systems. Acme Application Optimizers, anyone?
Posted by Addison Snell - June 5 @ 8:38PM
(Digg, Technorati, more)
There are 4 discussion items posted.
Submitted by $user.username on 06/09/2008 - 6:33AM
Multicore poses fundamental challenges for industrial HPC, but what you're observing highlights the importance of real physics, not cartoon physics. I'm expected to deliver performance, but above all I have to insure the physical realism that 10 or more years of development put in the code.
Even Wile E. Coyote couldn't devise a way to make the software life cycle keep pace with hardware. What we can do is strategic action to be sure we're somewhere else by the time the falling anvil hits.
Post #1
Submitted by $user.username on 06/10/2008 - 9:09AM
Addison - good post and none too soon.
The current workaround your research describes isn't sustainable b/c the added memory per processor is eating into the all too constrained power/flop ratio.
Unfortunately, the harsh reality is that the applications themselves will have to get more efficient.
eeeeegaaads! not that perhaps we need to introduce mini the mooch into this cartoon special
Post #2
Submitted by tuccillo on 06/11/2008 - 9:43AM
While the clock speed of the cores may not be increasing (much) with the continued rise in the number of cores per chip, the availability of more cores can result in increased performance for parallel applications. Of course, if your favorite application isn't parallelized using a message passing or threads approach or it's scalability is extremely limited then you are out of luck. I would argue that there are a substantial amount of message passing codes that do exhibit good scalability and their problem sizes are only getting larger (which should allow for the application of more cores). Clearly the trend is for more available cores so the pressure is on to improve scalability of your code if you need increased performance. The upcoming Intel Nehalem should address the rather disturbing trend towards less memory bandwidth per core as the number of cores per chip has increased.
Post #3
PGI Accelerator™ Fortran 95/03 and C99 compilers for x64+NVIDIA
Accelerate applications on x64+GPU platforms by adding OpenMP-like compiler directives to existing Fortran and C programs. Available now for Linux, MacOS and Windows. Download a free 15 day trial.
Platform HPC Workgroup Manager
Platform HPC Workgroup Manager integrates all the cluster productivity tools you need to deploy, run and manage your HPC environment.
Addison Snell is the CEO of InterSect 360 Research
More Addison Snell
Compairson to Core i7-980X by rsingle
HPC? not so much by ewahl
Re: IBM and HPC by truly64
HPC = servers but a lot more by lawries
Multi core deployment becomes a memory game by truly64
Re: Venture Capital Drought? Not So Much. by Ron Van Holst
Re: Podcast: Cray Awarded Defense Deal; SGI Makes Storage Buy; IBM Invents New Algorithm by Nastyanna
Painful Truth by jeffrey.mcallister
SGI = graphics + HPC by johnbarr
HPC = servers but a lot more by truly64
Oracle SPARC != Fujitsu SPARC by Alan M. Feldstein
Sun & HPC != Oracle & HPC by Merblich
a third vendor for lossless low latency 10GbE fabric by lee.fisher@hp.com
Response to GAH by KevinButerbaugh
Response to KevinButerbaugh by GAH
Response to KevinButerbaugh by GAH
Response to GAH by KevinButerbaugh
Response to bdrupp by KevinButerbaugh
Climate Crisis and Exaflops by bdrupp
Climate Crisis and Exaflops by John Hules
Climate Crisis and Exaflops by GAH
Climate Crisis by KevinButerbaugh
IBM "Brain Simulation" article is not properly presented. by Merritt
563 out of 1206 by vvolkov
Little Iron by gadunk
At least it's not "cloud" by KevinButerbaugh
Native QPI Interface? by commike
Mmmmmm by hellcats
New transistorized IC chip scales. by symmecon
Itanium at IDF by Alan M. Feldstein
Communication time by jnapper
"The financial meltdown and computing" by donpellegrino
Human Models by mdgabriel
High-End SPARC Chip for Scientific Applications by Alan M. Feldstein
RapidMind by Mr LolO
Rapidmind by dminor
Longer run times by JohnWest
re: Algo trading Angst by jshore
Results of Testing by in_the_crease
C-DAC announces plans for a petaflop system; IBM researchers are working on vertical integration techniques to extend Moore's Law another 15 years. We recap those stories and more in our weekly wrapup.
Read More...
The Moscow State University supercomputer, Lomonosov, has been selected for a high-performance makeover, with the goal of tripling its processing power to achieve petaflop-level performance in 2010. T-Platforms, who developed and manufactured the supercomputer, is the odds-on favorite to lead the project.
Read More...
Right on schedule, Intel has launched its Xeon 5600 processors, codenamed "Westmere EP." The 5600 represents the 32nm sequel to the Xeon 5500 (Nehalem EP) for dual-socket servers. Intel is touting better performance and energy efficiency, along with new security features, as the big selling points of the new Xeons.
Read More...
Mar 19 | OfficialWire | New super to support intelligence work Down Under. Read more...
Mar 18 | ChannelWeb | Westmere parts already showing up in HPC machines. Read more...
Mar 17 | The Register | But what about the tier ones? Read more...
Mar 17 | Cadalyst Magazine | A new generation of workstations is changing the nature of technical computing. Read more...
Mar 17 | Linux Magazine | Latest iteration of Sun Grid Engine able to tap into Cloud. Read more...
Jan 12 | | In-depth look at vSMP Foundation server virtualization technology, technical implementation, use cases and capabilities. The technical whitepaper provides an architectural overview and details on the three vSMP Foundation products: vSMP Foundation for SMP, vSMP Foundation for Cluster and vSMP Foundation for Cloud.
Jan 18 | | This white paper discusses Gore’s copper cable assemblies, and how they continue to exceed the standards for providing reliable, cost-effective solutions for high-performance computer applications.
Join this online panel discussion for live Q&A with leading industry experts, analysts, and end-users to discuss the latest innovations, best practices, barriers to implementation, and measurable benefits of server virtualization with a particular focus on today's real world solutions.
Learn about scalable fault-tolerant architectures and examples of energy efficient and scalable supercomputing clusters using dual QDR InfiniBand to combine capacity computing with network failover capabilities with the help of programming languages such as MPI and a robust Linux cluster management package.
LIVE@SCO9: The IBM team discusses new innovations in hardware, software and services that help clients better understand their workloads and get insight from their R&D efforts. Technology demonstrations include the soon-to-be-released Power7 HPC processor, the DCS990 system with 2.4 petabytes of storage, the xCAT management tool, secure HPC cloud computing and more. Winners of two HPCwire Readers' and Editors’ Choice Awards! Take the IBM virtual tour at SC09 or more information go online to: http://www-03.ibm.com/systems/deepcomputing/sc09.html