HPCwire: Can Big Blue Make Power7 Green?

The Leading Source for Global News and Information Covering the Ecosystem of High Productivity Computing

HPCwire >> Blogs

Blog: From the Editor

July 22, 2008

Can Big Blue Make Power7 Green?

In the past couple weeks, there has been a lot of buzz about the IBM's upcoming Power7 processors, which are slated to be used in NCSA's multi-petaflop "Blue Waters" supercomputer and Big Blue's HPCS PERCS system. Most of the recent speculation was stirred up by an article in The Register penned by Ashlee Vance, who supposedly got a hold of some internal IBM docs. According to Vance:

The IBM documents have the eight-core Power7 being arranged in dual-chip modules. So, that's 16-cores per module. As IBM tells it, each core will show 32 gigaflops of performance, bringing each chip to 256 gigaflops. Just on the gigaflop basis, that makes Power7 twice as fast per core as today's dual-core Power6 chips, although the actual clock rate on the Power7 chips should be well below the 5.0GHz Power6 speed demon.

In fact, according to Vance, the IBM literature says the chips will be shipped at 4.0 GHz, although I think that the CPUs headed for Blue Waters will most likely come in at between 3 and 4 GHz. This is quite a bit slower than the 4.7 GHz seen in IBM's current Power6-based 575 systems. The reason is obvious. To achieve the 10 petaflop peak performance (and one to two petaflops of sustained performance) that IBM is aiming for, the company will need to populate the machine with nearly 40,000 8-core Power7 processors. Even at the 45nm process technology node, the processor guys will be forced to ease up on the CPU clock to keep the chips from throwing off too much heat.

The bigger problem is that the IBM Power (not PowerPC) family is not known to be particularly energy efficient by today's standards. The architecture was originally designed for high levels of single thread performance, which is great for enterprise workloads, like database apps, but in the supercomputing arena, relying on single threaded performance is considered bad form. Building a practical petascale machine on the Power architecture is going to be a challenge.

Consider the latest Green500 stats. The top Power6-based 575 machines all come in at less than 100 megaflops/watt, which is only 1/4 as efficient as the Blue Gene/P supers and about 1/5 as efficient as Cell processor blade-based systems. A more sobering data point is that the IBM Power6-based 575 supercomputer at the European Centre for Medium-Range Weather Forecasts uses 1.3 megawatts to run the Linpack benchmark and achieves a modest 80 teraflops. Scaling this system up to a one Linpack petaflop would require over 16 megawatts. Keep in mind that's not peak power consumption, nor does it include cooling or storage.

If IBM maintains the roughly 100 watt TDP for the Power7 to match the current Power6 (and older Power5), then you're talking 4 megawatts just for the CPU hardware in Blue Waters. You can easily double that to figure the power consumption of the whole machine, which, according to The Register piece, will also include 620 TB of memory and 5 PB/sec of memory bandwidth. If you add in storage and cooling, you might have to double the power once again. Since Blue Waters will be water cooled, some extra energy efficiency will gained there, but I think NSCA will need something like 10 megawatts to feed their multi-petaflop beast.

If IBM could cut the Power7 TDP to, say, 50 watts, they and NCSA would be in much better shape. One option the chip designers may use to squeeze more energy efficiency from the silicon is to add some sort of floating point hardware acceleration. As Timothy Prickett Morgan of IT Jungle pointed out last week, the Power7 design does allow for such features:

...IBM's [Power7] roadmap and its top techies have been talking about an "advanced hybrid core design." I have been led to believe that by hybrid core, IBM means bringing special functions that used to be done on the motherboard our elsewhere in computer networks back onto the chip, but not necessarily inside the processor core. (Think of the VMX AltiVec vector math units or the decimal math units on the Power6 chip and you get the right idea.) This hybrid approach lets the Power core do the work it is designed to do--run applications--while these adjunct chips assist with specific functions.

Maybe a souped-up version of AltiVec/VMX (vector multimedia extension), which was introduced in the Power6, would help things along. IBM could also make use of the Cell SPE cores to get more parallelism on-chip. But this type of hardware would be considered quite exotic in the traditional enterprise space, where most of the Power7s will be sold.

Blue Waters is scheduled for boot up in 2010, so IBM still has a couple of years to figure out how to keep the lights from dimming at NCSA. And fortunately, the company has plenty of experience with low-power supercomputing; the PowerPC-based Blue Gene and the Cell-based Roadrunner are both tops in energy efficiency. It should be interesting to see what IBM finally comes up with.

Posted by Michael Feldman - July 22 @ 6:31PM

(Digg, Technorati, more)

Discussion

There are 0 discussion items posted.

Join the Discussion

You must be a registered user in order to comment on HPCwire stories.

Members enjoy:

	Access to Special Content, including Podcasts, Webcasts, and Whitepapers and more!
	Ability to take an active role in the discussions that are shaping the HPC technology discipline!
	Special offers available only to HPCwire members!

Become a Registered User Today!

Registered Users Log in Here to Comment

Email Address:	Password (case sensitive)

Remember me	Forgot Password?

Michael Feldman

Michael Feldman is the editor of HPCwire.

More Michael Feldman

Feature Articles

The Week in Review

C-DAC announces plans for a petaflop system; IBM researchers are working on vertical integration techniques to extend Moore's Law another 15 years. We recap those stories and more in our weekly wrapup.
Read More...

Moscow State University Supercomputer Has Petaflop Aspirations

The Moscow State University supercomputer, Lomonosov, has been selected for a high-performance makeover, with the goal of tripling its processing power to achieve petaflop-level performance in 2010. T-Platforms, who developed and manufactured the supercomputer, is the odds-on favorite to lead the project.
Read More...

Intel Ups Performance Ante with Westmere Server Chips

Right on schedule, Intel has launched its Xeon 5600 processors, codenamed "Westmere EP." The 5600 represents the 32nm sequel to the Xeon 5500 (Nehalem EP) for dual-socket servers. Intel is touting better performance and energy efficiency, along with new security features, as the big selling points of the new Xeons.
Read More...

Read more HPCwire features...

Top Headlines

Australia Commissions Cray Supercomputer

Mar 19 | OfficialWire | New super to support intelligence work Down Under. Read more...

Intel Partners See 'Easy' Upgrade Path With Xeon 5600 Chips

Mar 18 | ChannelWeb | Westmere parts already showing up in HPC machines. Read more...

AMD: OEMs primed for Opteron 6100s

Mar 17 | The Register | But what about the tier ones? Read more...

Arrival of the Desktop Supercomputer

Mar 17 | Cadalyst Magazine | A new generation of workstations is changing the nature of technical computing. Read more...

Scheduling HPC In The Cloud

Mar 17 | Linux Magazine | Latest iteration of Sun Grid Engine able to tap into Cloud. Read more...

Read more headlines...

Featured Whitepapers

Virtualization for Aggregation And The vSMP Architecture™

Jan 12 | | In-depth look at vSMP Foundation server virtualization technology, technical implementation, use cases and capabilities. The technical whitepaper provides an architectural overview and details on the three vSMP Foundation products: vSMP Foundation for SMP, vSMP Foundation for Cluster and vSMP Foundation for Cloud.

Copper Cable Technologies for High Performance Computing

Jan 18 | | This white paper discusses Gore’s copper cable assemblies, and how they continue to exceed the standards for providing reliable, cost-effective solutions for high-performance computer applications.

View the White Paper Library

Multimedia

Webcast: Virtualized Data Center Roundtable

Join this online panel discussion for live Q&A with leading industry experts, analysts, and end-users to discuss the latest innovations, best practices, barriers to implementation, and measurable benefits of server virtualization with a particular focus on today's real world solutions.

Webcast: Watch SC09 Birds of a Feather Video: Scalable Fault-Tolerant HPC Supercomputers

Learn about scalable fault-tolerant architectures and examples of energy efficient and scalable supercomputing clusters using dual QDR InfiniBand to combine capacity computing with network failover capabilities with the help of programming languages such as MPI and a robust Linux cluster management package.

Webcast: High Performance Computing for a Smarter Planet

LIVE@SCO9: The IBM team discusses new innovations in hardware, software and services that help clients better understand their workloads and get insight from their R&D efforts. Technology demonstrations include the soon-to-be-released Power7 HPC processor, the DCS990 system with 2.4 petabytes of storage, the xCAT management tool, secure HPC cloud computing and more. Winners of two HPCwire Readers' and Editors’ Choice Awards! Take the IBM virtual tour at SC09 or more information go online to: http://www-03.ibm.com/systems/deepcomputing/sc09.html