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March 24, 2006
Cray's Adaptive Supercomputing - A Paradigm Shift
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"Adaptive supercomputing will cause a paradigm shift in the way users select and use HPC systems. Adaptive supercomputing is necessary to support the future needs of HPC users as their need for higher performance on more complex applications outpaces Moore's Law. The Cray motto is: adapt the system to the application - not the application to the system," says Steve Scott, CTO of Cray Inc., March 2006.
This past week Cray announced their vision of "Adaptive Supercomputing," the company's long-range HPC technology strategy. Steve Scott, CTO of Cray, briefed me about this strategy and I'd like to share with you, in broad terms, what he said.
The increasing demand for better performance can no longer be achieved through processor improvements predicted by Moore's law and a one-size-fits-all mentality. HPC users are no longer getting the performance advances they need from microprocessors. Commercial response to the slowdown in Moore's law has been to provide multi-core chips. These are general-purpose architectures, optimized for most widely used applications. But as it is widely recognized, when scientific computing migrated to commodity platforms, interconnect performance, both in terms of bandwidth and latency, became the limiting factor on overall application performance and remains a bottleneck to this day.
If one takes an example from Earth sciences: Users wish to perform simulations on coupled climate models, such as ocean, atmosphere, biosphere and solid earth. [NASA Report; Earth Sciences Vision 2030]. Currently, these models are designed to run on only one processor architecture (e.g., scalar or vector). However, an increase in both model complexity and number of components lends itself to a variety of processing technologies. With this new approach, applications can have dramatically shorter time scales to completion. The goal is to tie these models together and exchange data.
Another example is from Computer Aided Engineering (CAE). Industry is pushing the limits on the size of the problem and its complexity. Model sizes of CAE, are currently limited by computational and data storage capabilities. Moving to multi-physics simulations and modeling real-world behavior requires coupling previously independent simulations. A full system analysis requires a system with orders of magnitude better performance, since one needs to examine the behavior of composite materials at micro-scale and real-time stress-strain behavior at macro-scale.
The CAE example above was used as a Grand Challenge Case Study in a recent report on High Performance Computing & Competitiveness, sponsored by the Council on Competitiveness in the USA. The report states: "The next high-payoff high performance computing grand challenge is to optimize the design of a complete vehicle by simultaneously simulating all market and regulatory requirements in a single integrated computational model."
After exhaustive analysis Cray Inc. concluded that, although multi-core commodity processors will deliver some improvement, exploiting parallelism through a variety of processor technologies using scalar, vector, multithreading and hardware accelerators (e.g., FPGAs or ClearSpeed co-processors) creates the greatest opportunity for application acceleration.
Adaptive supercomputing combines multiple processing architectures into a single scalable system. From the user's point of view, one has the application program, which uses libraries, tools, compilers, scheduling system management and a runtime system. Then comes the adaptive software, a compiler, which knows what types of processors are available on the heterogeneous system and targets code to the most appropriate processor. In certain cases, at run-time, the system will determine the most appropriate processor for running a piece of code, and direct the execution accordingly. As Scott said: "Adapt the system to the application - not the application to the system."
Cray's roadmap to adaptive supercomputing will unfold in phases. Phase 0 represents the current generation. They have individual architecture systems: The Cray XT3 - MPP scalar, the Cray X1E - Vector, the Cray MTA - Multithreaded, and Cray XD1 - AMD Opteron plus FPGA accelerators.
Phase 1, codenamed "Rainer," will create an integrated user environment across all of Cray's platforms. In Phase 2, Cray plans integrated multi-architecture systems. These are currently codenamed "Eldorado" (upgraded Cray XT3 technology plus multithreading) and "Black Widow" (upgraded Cray XT3 technology plus vector processors) scheduled to become available in 2007. All of these platforms will use AMD Opterons for their scalar processor base.
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