HPCwire: Thomas Sterling Speaks to the Future of HPC

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June 09, 2006

Thomas Sterling Speaks to the Future of HPC

by Christopher Lazou, HiPerCom Consultants, Ltd.

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At the recent NEC User Group meeting in Toronto Canada, Thomas Sterling gave a keynote address to share his thoughts about some of the key challenges facing the high performance computing community. At the event, contributing editor Christopher Lazou caught up with Sterling, where they discussed these challenges and talked about some possible solutions.

Lazou: Thomas, it's good that you can spare some of your valuable time to talk to me. We meet again this time at the annual NEC users group meeting, this year in Toronto, Canada, with an eclectic group of users of true supercomputing. As a keynote speaker, you are the man of the moment. Glancing at your many hats you wear, one can see you have a number of important roles and long experience in computer architecture research, so lets briefly discuss some of the burning issues concerning HPC and in the process try to gain an insight of your views and share them with the HPC community.

Last year you moved to LSU as Professor at the Department of Computer Science focusing on HPC systems architecture research. Can you briefly describe the key areas of research your team is concentrating on? Would this work be of benefit to HPC in the short term or is it blue-sky research?

Sterling: We are currently exploring key challenges of a new class of computer architecture to confront efficiency, scalability, power and reliability. This requires a paradigm shift of execution and programming models. There is a desperate need for intrinsic latency hiding mechanisms to be incorporated in the infrastructure of programming and runtime resource management.

We are developing a new model for computing called "ParalleX", extending our earlier work in processor in memory (PIM), and combining these with new work in static dataflow to provide a new class of architecture that adaptively responds to variations in temporal locality. The short-term impact is that the execution model has a spin off of a programming methodology that can operate on conventional architecture. It should improve latency hiding and scalability. In some small way, this work is already influencing projects sponsored by the DoE, as part of the Fast OS project and by the NSF project (NGST).

Lazou: Is there any Federal investment in innovative high-risk computer architecture R&D?

Sterling: There is very little Federal funding for this type of research activity. There were recently several studies, which concluded that the HPC architecture research pipeline is empty. Examples of such studies include the National Academy of Science report, and the HECRTF and PITAC studies. The possible exception is the DARPA HPCS program, but you asked about "high risk" and it is not clear that HPCS falls in to that category. With respect to my own work that you asked about, I have Federal support for some relevant software projects. And, until recently NASA was sponsoring the hardware research but this funding ended last March. A small system architecture study is underway by NASA in which I am involved, as well. Elsewhere, there is some other good work being supported in FPGA-based computing and work at Stanford, University of Texas, and University of Washington. Hopefully, there will be new energy and direction from the agencies in the near future. Certainly it is in the best interest of their respective missions and that of the nation to reinvigorate such valuable explorations.

Lazou: In the next five years, silicon would be the material for high-end computer chips. Can architecture changes extend silicon life to say another five years?

Sterling: Yes. The research mentioned above at several universities could lead to significant improvements in the use of current generation silicon technology and suggests approaches to extending the useful life of silicon for general purpose computing down to near nano-scale. The work I and my collaborators are doing could constructively impact on this as well, so long as vendors accept the challenge and implement demonstrated improvements. Vendors cannot be expected to take the risk in a domain of such uncertainty. Rather, Federal funding should be used to explore the space of possible approaches and determine which concepts are viable. We are making poor use of silicon today compared to what it is capable of. I believe that new architectures can give us performance improvements of one to two orders of magnitude from what we get today. The IBM/Sony Cell architecture, for example, hints at the possibilities.

Lazou: What is the most promising material expected to replace silicon for supercomputing chip production?

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