HPCwire: Intel Threads Its Way to Parallel Programming

The Leading Source for Global News and Information Covering the Ecosystem of High Productivity Computing

HPCwire >> Features

September 01, 2006

Intel Threads Its Way to Parallel Programming

by Michael Feldman, Editor, HPCwire

Page: 1 of 3
1 | 2 | 3 All »

As computer systems with multiple CPUs become spread across the IT landscape, programmers will need a new set of development tools to take advantage of this new hardware model. This week, Intel announced a new high-level threading library aimed at software developers who are looking to exploit the parallelism of multi-core and multi-processor SMP systems. The new product, called Threading Building Blocks (TBB), extends C++ to provide thread-level parallelism for shared memory platforms based on x86 and Itanium processors. Intel also announced upgraded versions of its Thread Checker and Thread Profiler products, which will work in conjunction the new TBB product.

Intel's threading software products are part of the company's overall strategy to keep software applications in sync with the multi-core processors that are becoming mainstream in the marketplace. The chipmaker is highly motivated to make it easier for software developers to program those new chips since Intel is predicting that nearly all of the microprocessors it ships will be multi-core by the end of 2007. It's worth noting that AMD processors will get a free ride with TBB, since the x86 targeted code will work transparently with AMD's x86 offerings.

According to James Reinders, Intel marketing director for the company's Developer Products Division, his group has a fair amount of experience with multi-core and multi-processor software development, at both the very high end in high performance computing -- with some of their tools for MPI -- and in the workstation and server environments.

"That experience gives us an understanding of the challenges that the industry and we face when you look at the problem of exploiting parallelism," says Reinders. "I have no doubt that this transformation is going to happen. In fact, I'm very confident that ten years from now, virtually every programmer is going to say that they understand and think about parallelism."

But Reinders also understands there are very significant challenges that need to be understood. One of them is scalability: Can you get an 8X performance increase when you go from two threads to sixteen? Another has to do with a new set of problems that threading introduces, specifically, deadlocks and race conditions.

"The third big challenge is ease of programming," says Reinders. "Right now, some of the ways of introducing threading add a lot of complexity to a program. And we don't believe that's necessary. But it's just a fact of life when you're dealing with programming languages that haven't been extended or that don't comprehend parallelism."

C++ is one such language. TBB extends C++ via a run-time library that uses the language's template feature to abstract parallel programming constructs. The run-time library invokes the low-level thread and mutex capabilities of the target operating system to provide high-level thread management. This allows C++ developers to perform parallel programming without having to be concerned with native thread management or the maintenance of critical regions. The thread library API is portable across Linux, Windows, or Mac OS platforms (although, in version 1.0, support for 64-bit x86 is missing for Mac OS and Itanium is only supported on Linux). The TBB run-time library is royalty free, so with a single unit price of $299, ISVs can ship as many applications as they want without having to give Intel a piece of the action.

Using TBB to implement parallelism results in a much smaller amount of source code as compared to a native thread implementation. In the latter case, the application-specific algorithms can get lost in all the code devoted to thread management and breaking up the problem.

"At the end of the day, you may have over three quarters of your code devoted to managing threads," observes Reinders. "That's overwhelming. I do not believe we will succeed if we tell people that they need to write all this [code] to take advantage of threading."

The template library supplies a broad set of generic parallel algorithms -- simple ones, like fors and reduces, and more complex ones, like whiles and pipelines. The library also provides an abstraction for thread-safe containers -- data structures (e.g., hash maps, vectors and queues) that are protected from mutual access by multiple threads. This frees the developer from having to explicitly create them and then enforce their protection with mutexes. Interfaces to low-level features like atomic operations, scalable memory allocation, locks and mutexes are also supplied in the library.

Page: 1 of 3
1 | 2 | 3 All »

Article Tools

Share Options

(Digg, Technorati, more)

Subscribe

Subscribe to HPCwire

Discussion

There are 0 discussion items posted.

Join the Discussion

You must be a registered user in order to comment on HPCwire stories.

Members enjoy:

	Access to Special Content, including Podcasts, Webcasts, and Whitepapers and more!
	Ability to take an active role in the discussions that are shaping the HPC technology discipline!
	Special offers available only to HPCwire members!

Become a Registered User Today!

Registered Users Log in Here to Comment

Email Address:	Password (case sensitive)

Remember me	Forgot Password?

RSS Feeds

Feeds by Topic

Feeds by Industry

Feeds by Content Type

Top Headlines

AMD: OEMs primed for Opteron 6100s

Mar 17 | The Register | But what about the tier ones? Read more...

Arrival of the Desktop Supercomputer

Mar 17 | Cadalyst Magazine | A new generation of workstations is changing the nature of technical computing. Read more...

Scheduling HPC In The Cloud

Mar 17 | Linux Magazine | Latest iteration of Sun Grid Engine able to tap into Cloud. Read more...

Tailoring Medicine with Supercomputers

Mar 16 | Bio-IT World | Biotech firm builds genetic models from patient data. Read more...

Gelsinger Stuns Analysts and Colleagues with Storage Pool Plan

Mar 15 | The Register | EMC's grand vision for unified global storage. Read more...

Read more headlines...

Featured Whitepapers

Virtualization for Aggregation And The vSMP Architecture™

Jan 12 | | In-depth look at vSMP Foundation server virtualization technology, technical implementation, use cases and capabilities. The technical whitepaper provides an architectural overview and details on the three vSMP Foundation products: vSMP Foundation for SMP, vSMP Foundation for Cluster and vSMP Foundation for Cloud.

Copper Cable Technologies for High Performance Computing

Jan 18 | | This white paper discusses Gore’s copper cable assemblies, and how they continue to exceed the standards for providing reliable, cost-effective solutions for high-performance computer applications.

View the White Paper Library

Multimedia

Webcast: Virtualized Data Center Roundtable

Join this online panel discussion for live Q&A with leading industry experts, analysts, and end-users to discuss the latest innovations, best practices, barriers to implementation, and measurable benefits of server virtualization with a particular focus on today's real world solutions.

Webcast: Watch SC09 Birds of a Feather Video: Scalable Fault-Tolerant HPC Supercomputers

Learn about scalable fault-tolerant architectures and examples of energy efficient and scalable supercomputing clusters using dual QDR InfiniBand to combine capacity computing with network failover capabilities with the help of programming languages such as MPI and a robust Linux cluster management package.

Webcast: High Performance Computing for a Smarter Planet

LIVE@SCO9: The IBM team discusses new innovations in hardware, software and services that help clients better understand their workloads and get insight from their R&D efforts. Technology demonstrations include the soon-to-be-released Power7 HPC processor, the DCS990 system with 2.4 petabytes of storage, the xCAT management tool, secure HPC cloud computing and more. Winners of two HPCwire Readers' and Editors’ Choice Awards! Take the IBM virtual tour at SC09 or more information go online to: http://www-03.ibm.com/systems/deepcomputing/sc09.html