HPCwire: New NSF Center Targets Reconfigurable Computing

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November 03, 2006

New NSF Center Targets Reconfigurable Computing

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Under the auspices of the highly acclaimed program for Industry/University Cooperative Research Centers (I/UCRC) at the National Science Foundation (NSF), the Center for High-Performance Reconfigurable Computing (CHREC, pronounced "shreck") is a new national center and consortium for fundamental research in reconfigurable computing. CHREC is comprised of approximately two-dozen (and growing) organizations from academia, industry, and government with synergistic interests and goals in this field. Having recently completed a two-year development, review, and selection process at NSF, CHREC becomes operational in January 2007.

Recently we got the opportunity to ask Dr. Alan George, the CHREC director, to explain the significance of the new NSF center and help us understand the type of work that will be performed there.

HPCwire: What is the focus of the work at CHREC?

George: High-performance reconfigurable computing, the focus of CHREC, holds tremendous promise in addressing the needs of a broad range of applications, in areas such as signal and image processing, cryptology, communications processing, data and text mining, optimization, bioinformatics, and complex system simulations. Reconfigurable systems span a variety of platform types, from leading-edge machines on earth to mission-critical machines in space. Advantages from a reconfigurable approach can be realized in terms of performance, power, size, cooling, cost, versatility, scalability, and dependability to name a few important facets where conventional computing infrastructure alone is proving unable to meet the needs of an increasing number of critical applications. Preliminary thrust areas for CHREC include device and core building blocks, reconfigurable systems and services, design automation and programming methods and tools, and reconfigurable and parallel algorithms and applications. Research projects in these areas are formulated on an annual basis in concert with Center partners, emphasizing a keen interest in exploring and evaluating new methods as well as key tradeoff analyses.

HPCwire: What are the main goals of CHREC?

George: A broad range of goals have been defined with NSF for CHREC, including: (1) Establish the nation's first multidisciplinary research center in reconfigurable high-performance computing as a basis for long-term partnership and collaboration amongst industry, academe, and government; (2) Directly support the research needs of industry and government partners in a cost-effective manner with pooled, leveraged resources and maximized synergy; (3) Enhance the educational experience for a diverse set of high-quality graduate and undergraduate students; and (4) Advance the knowledge and technologies in this emerging field and ensure relevance of the research with rapid and effective technology transfer.

HPCwire: Why is the field of reconfigurable computing so important to HPC?

George: Although a relatively new field, reconfigurable computing (RC) has come to the forefront as an important processing paradigm for HPC, often in concert with conventional microprocessor-based computing. With RC, the full potential of underlying electronics in a system may be better realized in an adaptive manner. At the heart of RC, field-programmable hardware in its many forms has the potential to revolutionize the performance and efficiency of systems for HPC as well as deployable systems in high-performance embedded computing (HPEC). One ideal of the RC paradigm is to achieve the performance, scalability, power, and cooling advantages of the "Master of a trade," custom hardware, with the versatility, flexibility, and efficacy of the "Jack of all trades," a general-purpose processor. As is commonplace with components for HPC, such as microprocessors, memory, networking, storage, etc., critical technologies for RC can also be leveraged from other IT markets to achieve a better performance-cost ratio, most notably the field-programmable gate array or FPGA. Each of these devices is inherently heterogeneous, being a predefined mixture of configurable logic cells and powerful, fixed resources.

HPCwire: What do you think are the biggest opportunities and challenges in this area?

George: Many opportunities and challenges exist in realizing the full potential of reconfigurable hardware for HPC. Among the opportunities offered by field-programmable hardware are a high degree of on-chip parallelism that can be mapped directly from dataflow characteristics of the application's defining parallel algorithm, user control over low-level resource definition and allocation, and user-defined data format and precision rendered efficiently in hardware. In realizing these opportunities, there are many vertical challenges, where we seek to bridge the semantic gap between the high level at which HPC applications are developed and the low level (i.e. HDL) at which hardware is typically defined. There are also many horizontal challenges, where we seek to integrate or marry diverse resources such as microprocessors, FPGAs, and memory in optimal relationships, in essence bridging the paradigm gap between conventional and reconfigurable processing at various levels in the system and software architectures.

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