HPCwire: 17th Machine Evaluation Workshop at Daresbury

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December 15, 2006

17th Machine Evaluation Workshop at Daresbury

-- The Impact of Multi-Core Chips on Clusters

by Christopher Lazou, HiPerCom Consultants, Ltd.

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On December 4th through 6th, 2006, about 250 people (around the same as last year) attended the 17th machine evaluation workshop at CCLRC Daresbury Laboratories, UK. This excellent workshop, in its seventeenth year, is a leading UK national event dedicated to distributed, high performance scientific computing. The principle objective is to encourage close contact between the research communities from the Mathematics, Chemistry, Physics, Engineering and Materials Programmes of EPSRC and the major vendors of mid-range computing systems, workstations, servers, software and peripherals. An increase in academic participation reflected a growing participation from researchers from the other communities, notably from the Natural Environment Research Council (NERC) and Particle Physics & Astronomy (PPARC) Research Council.

Most of the 25 presentations were from vendors, describing their own products on topics such as hardware, compilers, graphics, storage and networking. They focused on cluster solutions, based on commodity chips, interconnect networks and associated file storage systems. An important component of the workshop is the availability of systems for benchmarking evaluation purposes.

In addition, during this year's event there were three parallel, informal breakout sessions. These were focussed on special interest areas, with invited speakers to open the sessions, and have been designed to encourage lively debates, as well as highlight developments and showcase performance features of tools. The breakout sessions' themes were (1) novel architectures (e.g. FPGAs, Cell); (2) software developments enabling higher performance; and (3) Gigabit Ethernet as a high performance interconnect.

There were nineteen companies exhibiting, keen to promote their readymade products, including those based on AMD Opteron, Intel 'Woodcrest' and the Intel Itanium 2 processors. A strong presence of AMD Opteron and Intel 'Woodcrest', dual-core and early quad-core systems, as well as various models of blade products, were on display and available for demonstrations.

Of course other factors often dominate the selection of systems. For example, one trade-off is price/performance. Another is the type and size of application the system is purchased for. This is pertinent especially for commodity clusters and the selection of interconnect fabric. One suspects it depends on how the Total Cost of Ownership (TCO) integral is constructed.

Crispin Keable (IBM) gave a talk titled "And We Also Do Hardware," describing the three strands IBM is currently pursuing under the Deep Computing umbrella. He reminded the audience that Deep Computing combines a number of techniques -- advanced mathematics, domain specific knowledge and software specialisation -- to solve extremely complex problems in this sea of digital data. He unconsciously invoked the sentiments from IBM's Quaker progeny by claiming that their strategy is good for the customer, good for the world and good for IBM.

Crispin was frank, recognising that sustained performance and scaling is not very high compared to Linpack. The challenge facing the industry is not only system design, for scalability, power consumption, weight and space, but also software -- operating systems, compilers, tools, application porting and licensing.

IBM is tackling these issues with the realization that one size does not fit all. The Power based product line provides advanced systems based on loosely coupled clusters. With the recent $244 million HPCS award (equivalent to roughly 2,440 person years -- some would say R&D subsidy) this line is expected to culminate in the Power7 to be used in the PERCS petaflops system.

Research collaborations on the Blue Gene/L architecture and the Cell BE multi-core system on a chip were also briefly described. These included the Blue Brain project, which is researching new insights into how the human brain works. The work could be important for the treatment of debilitating diseases such as schizophrenia, autism and Alzheimer's. Using the Cell BE for heart modelling was presented as another example of research collaboration. The Cell BE chip is also being used as the co-processor (accelerator) on the Roadrunner petaflops system at Los Alamos National Laboratory.

Both Blue Gene/L and Cell BE are examples of experimental technologies moving into niche domains and gradually becoming mainstream. IBM believes that next generation chip designs are focusing on high performance/power consumption ratios and that semiconductor power trends are driving future systems. With hundreds of thousands of processors, software development environments will be severely challenged. Issues such as reliability and fault tolerant management systems, to vitiate MTBF effects, represent additional challenges.

As in previous years, the Daresbury Benchmark results were of great interest. These consisted of a plethora of both serial and distributed memory benchmark results, compiled by Martyn Guest and his team from Daresbury. The benchmarks from many systems, including the latest products from vendors using their latest multi-core chips, were presented. The serial component of the benchmark suite, used to obtain these results, consists of many computational chemistry kernel codes, molecular dynamics, Quantum Monte Carlo, Jacobi Solver, STREAM -- measured sustainable memory bandwidth in HPC (TRIAD), plus the ab initio molecular electronic structure package GAMESS-UK and the parallel molecular dynamics benchmark, DL_POLY. The results from SPECfp2000, SPECInt2000, HPC Challenge and other well-known benchmarks were also presented.

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