HPCwire: Heterogeneous Processing In The Age Of Nanocore (Part I)

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August 24, 2007

Heterogeneous Processing In The Age Of Nanocore (Part I)

by the High-End Crusader

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In a series of three articles, the High-End Crusader ponders the future impact of industry's ever-evolving many-core technology on both parallel computing and heterogeneous processing. In the first article, he explains the meltdown of monolithic, monothreaded, out-of-order scalar processors as vehicles for delivering steadily increasing performance.

The high-end computing community needs to reconceptualize both parallel computing and heterogeneous processing in tandem with industry's unsteady progression from multicore infancy to many-core adolescence to the full maturity of nanocore.

Nanocore is a notional scaling range for the number of cores in a chip multiprocessor. The low end of the range is the inflection point, sometime after 64 cores, when wholly innovative microarchitectural strategies are required to scale further. The high end of the range is the time, perhaps in 2014, when we can integrate 1,024 cores on a single processor die.

The conventional justification of heterogeneous processing, which has much to recommend it, is that distinct processor types, with distinct core execution models, can produce higher execution efficiencies on modern applications comprised of disparate subcomputations with disparate algorithmic characteristics and thus disparate architectural needs. Standard metrics of execution efficiency include operations per second per dollar and operations per second per watt. A slogan that nicely captures this line of thinking is, make the common parallelism case fast and low power, tightly integrate all parallelism cases so that there is minimum overhead in "switching" among them, and scale to the heavens, which goes nicely with execution efficiency.

Note that "tight integration" is first and foremost tight integration among the disparate cores on a heterogeneous processor die.

On occasion, provision is made for locality. For example, there is an admirable special-purpose machine in development that optimizes short-range communication at the expense of long-range communication, targeting strongly localizable applications. In contrast, a general-purpose heterogeneous-processing system achieves high execution efficiencies on a broad range of applications, no matter what their parallelism or locality characteristics.

Another observation is that the vast cloud of systems collectively known as "high-performance computers" has bifurcated into two effectively disjoint sets, depending on whether government funding is driving performance regimes well above any level the private sector would consider a market sweet spot.

This sweet spot is constantly evolving; it might be anywhere from a few tens to a few hundreds of sustained TFs/s in 2011. Pseudo-commercial super clusters are red herrings that obscure this clear picture.

Be this as it may, only a handful of systems are scaling ambitiously. The reference machine is, of course, Japan's Keisoku Keisanki, which is running in the Riken lab today at 2 PFs/s. This is a machine whose heroic _useful_ scalability is due to brilliantly engineered integration of heterogeneous processors. Here is the break down of its 10 PFs/s. First, 1.5 PFs/s comes from (presumably out-of-order) scalar processors. Then, there is another 0.5 PFs/s coming from vector processors. Finally, the heavy lifting is done by "Grape-7", which is an array of identical special-purpose devices (SPD) specially optimized for finite-element analysis. This SPD array makes up the remaining
8 PFs/s.

Sustained performance will be remarkably high on each of 21 preselected applications.

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