HPCwire: High Performance 3D Image Reconstruction Platforms

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October 26, 2007

High Performance 3D Image Reconstruction Platforms

-- State of the Art, Implications and Compromises

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by Prof. Dr. Marc Kachelrieß, Professor for Medical Imaging, Institute of Medical Physics (IMP), University of Erlangen-Nuremberg, Germany and Olivier Bockenbach, Systems Engineer, Mercury Computer Systems, Berlin, Germany

High-resolution tomographic scanners and other 3D technologies provide a number of compelling advantages for diagnostic medical imaging. However, 3D modalities such as Computed Tomography (CT) and Magnetic Resonance Imaging (MRI) are creating ever larger volumes of data, increasing the need for faster and bigger servers, higher network bandwidth, workstations with large memory and fast graphics, as well as advanced diagnostic software.

Advanced 3D Multi-Slice CT scanners generate up to more than 2000 projections per second, thus increasing the need for high-performance platforms that allow for the reconstruction and processing of medical imaging data nearly in real-time. High-performance systems, such as those based on the Cell Broadband Engine processor technology, allow for the implementation of advanced analytical and statistical CT reconstruction algorithms (and more specifically backprojection algorithms), thus enhancing image quality while keeping the X-Ray exposure of the patient as low as possible.

Tomographic image reconstruction is computationally very demanding. In all cases the backprojection represents the performance bottleneck due to the high operational count and due to the high demand placed on the memory subsystem. In the past, solving this problem has led to the use of digital signal processors and the implementation of specific architectures, connecting Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) to the memory through dedicated high-speed busses. More recently, attempts have also been made to use Graphic Processing Units (GPUs) and the Cell processor.

However much these architectures differ, they all share common properties that make them attractive for the implementation of backprojection algorithms: the relative balance of high memory bandwidth and processing capabilities. On the other hand, harnessing the power of such devices necessarily also involves decision making with regard to the computational precision, the handling of the signal dynamics and the allowed approximations one can consider for making efficient use of the processing power of these devices.

Once a valid solution for the implementation of a 3D backprojection algorithm has been found for the device under consideration, there are major tasks to be addressed before the algorithm-device pair can be successfully deployed in a medical Image Reconstruction System (IRS).

The backprojection is a considerable processing step, but a 3D image reconstruction algorithm also includes pre-processing, filtering and post-processing steps. Various devices considered for accelerating the backprojection reveal themselves to be more or less usable for other tasks, requiring more or less assistance from other co-processing units. The implementation of the complete reconstruction pipeline may require the combination of several different devices, influencing the design, implementation and maintenance costs. However broad the spectrum of possible solutions may be, clinical and hospital operating conditions place another constraint on the IRS. These requirements are mainly directed towards processing speed, in order to match the hospital workflow. Nevertheless, the operating environment also includes processing density, as well as power and cooling requirements. The expected level of availability also places another constraint on the IRS.

Finally, more and more attention is being paid to the costs of the IRS, not only during the design but also over the complete life cycle of the IRS. Hence, there are multiple aspects that need to be taken into consideration, such as the life cycle of the underlying technology, the rate at which new devices are introduced and the end of life, together with the level of compatibility that is offered among devices from the same vendor or product family.

Hardware platforms

The aim of this investigation is to implement a 3D cone-beam perspective backprojection algorithm for the Cell processor and to benchmark its performance against other alternatives, such as PC-, FPGA- or GPU-based implementations. Four different platforms were selected:

the reference platform for image quality is on a standard PC with a single Xeon processor clocked at 3.06 GHz and a front bus side with 533 MHz
the PCI Express Cell Accelerator Board from Mercury Computer Systems
the PCI VantageRT-FCN board from Mercury Computer Systems
the G70 GPU from NVIDIA.

Implementation principles

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