The Leading Source for Global News and Information Covering the Ecosystem of High Productivity Computing
March 14, 2008
Image processing appears in numerous application domains, including video transcoding, medicine, mapping, inspection, photography, and document processing. Due to the proliferation of image sensors and high-resolution displays, digital image processing is a staple on everything from cell phones to supercomputers.
However, whatever the hardware platform, the performance of image processing applications can significantly affect their usefulness and the user experience. Multi-core processors and many-core accelerators offer many new opportunities for radically improved performance in the area of digital imaging. Achieving maximum performance on these processors, however, requires a parallel implementation and, due to the large amount of data processed, efficient use of the memory system. In this article, we will consider a range of digital image processing applications and will discuss how they can be efficiently implemented on multi-core processors using a pattern-based approach and the use of a development platform that can translate these patterns directly into machine language.
High performance image processing has been a key enabler for many new products. Computation can be used to overcome noise limitations for handheld cameras (enabling the use of a less expensive sensor), can be used to achieve high compression rates (enabling video to be used over low bandwidth network connections), or can be used to extract metadata from images (enabling them to be indexed in a database). In fact, the use of image processing has been used to correct for diffraction effects in optical lithography masks, enabling the electronic industry itself to produce the extremely dense multi-core processors we are addressing here!
Image processing is also extremely important in the consumer space. In particular, image processing can be used to dramatically extend the capabilities of handheld photography. It can be used to reduce noise, allowing low-light photography; to create panoramas by registering and blending multiple images; to create high-dynamic range images by combining multiple exposures; to automatically focus on faces and to compensate for vibration; and to dramatically improve shots taken using natural lighting by combining them with more detailed images taken with a flash.
The keys to performance are the exploitation of parallelism and data locality. Fortunately, many image processing algorithms are based on a relatively small number of patterns of computation. Each of these patterns has a certain amount of latent parallelism and data locality. Since different processors have different mechanisms for expressing parallelism and data locality, different optimizations may be required on different systems. However, a software development platform can still exploit these patterns if image processing algorithms are expressed in terms of them. Such an approach can significantly reduce implementation complexity and costs.
Image processing algorithms can basically be classified into the map, stencil, spectral, and segmented computational patterns:
It should be noted that these are patterns, not library functions. Patterns are more about how data is accessed and managed and how tasks are applied to that data rather than about particular computations. Many possible computations can be implemented under every pattern, and image processing applications often involve a complex composition of these patterns.
The number of patterns required is surprisingly small. However, even the simplest pattern does require some processor-specific optimizations for maximum performance. Consider the map pattern. Even this "trivial" parallel pattern can benefit from blocking up operations and using these blocks to perform loop unrolling and vectorization, as well as the use of cache management strategies such as alignment, prefetching, and double buffering. Since operations may be composed, the per-element operation used in the map pattern may become arbitrarily complex, and in particular may not take a constant amount of time to execute. In this case load balancing is also required.
Other patterns require more complex optimizations. For example, in order to implement the stencil pattern effectively, data read into the processor's on-chip memory for one stencil's neighborhood should be reused, whenever possible, in other computations for which it is needed. One useful implementation strategy on a serial machine is a sliding window. On a parallel machine, tiled sliding windows can be used, but their geometry should be chosen to avoid false sharing and other negative cache effects while achieving load balancing and good alignment. When multiple opportunities for exploiting parallelism are available in the hardware, implementing high-performance versions of even these seemingly simple patterns using traditional low-level approaches can result in very complex and error-prone code.
One approach is to use a framework that embodies these patterns and allows their composition. While a framework makes it easy to write sophisticated applications quickly, it does not provide the ultimate in performance since typically only limited amounts of low-level optimization can be performed automatically. This is because a framework is "on top" of machine language implemented using a traditional compiled serial language. The framework does not have access to the finer grained versions of parallelism that only a system directly manipulating machine language can target. Conversely, with a framework the compiler sees only the serial code used to implement the framework and not the parallelism intrinsic to the pattern. A framework can also add significant amounts of overhead, depending on its implementation.
Page: 1 of 2(Digg, Technorati, more)
PGI Accelerator™ Fortran 95/03 and C99 compilers for x64+NVIDIA
Accelerate applications on x64+GPU platforms by adding OpenMP-like compiler directives to existing Fortran and C programs. Available now for Linux, MacOS and Windows. Download a free 15 day trial.
Platform HPC Workgroup Manager
Platform HPC Workgroup Manager integrates all the cluster productivity tools you need to deploy, run and manage your HPC environment.
Mar 19 | OfficialWire | New super to support intelligence work Down Under. Read more...
Mar 18 | ChannelWeb | Westmere parts already showing up in HPC machines. Read more...
Mar 17 | The Register | But what about the tier ones? Read more...
Mar 17 | Cadalyst Magazine | A new generation of workstations is changing the nature of technical computing. Read more...
Mar 17 | Linux Magazine | Latest iteration of Sun Grid Engine able to tap into Cloud. Read more...
Jan 12 | | In-depth look at vSMP Foundation server virtualization technology, technical implementation, use cases and capabilities. The technical whitepaper provides an architectural overview and details on the three vSMP Foundation products: vSMP Foundation for SMP, vSMP Foundation for Cluster and vSMP Foundation for Cloud.
Jan 18 | | This white paper discusses Gore’s copper cable assemblies, and how they continue to exceed the standards for providing reliable, cost-effective solutions for high-performance computer applications.
Join this online panel discussion for live Q&A with leading industry experts, analysts, and end-users to discuss the latest innovations, best practices, barriers to implementation, and measurable benefits of server virtualization with a particular focus on today's real world solutions.
Learn about scalable fault-tolerant architectures and examples of energy efficient and scalable supercomputing clusters using dual QDR InfiniBand to combine capacity computing with network failover capabilities with the help of programming languages such as MPI and a robust Linux cluster management package.
LIVE@SCO9: The IBM team discusses new innovations in hardware, software and services that help clients better understand their workloads and get insight from their R&D efforts. Technology demonstrations include the soon-to-be-released Power7 HPC processor, the DCS990 system with 2.4 petabytes of storage, the xCAT management tool, secure HPC cloud computing and more. Winners of two HPCwire Readers' and Editors’ Choice Awards! Take the IBM virtual tour at SC09 or more information go online to: http://www-03.ibm.com/systems/deepcomputing/sc09.html