HPCwire: Intel Adds Some Detail to Their Roadmap

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March 21, 2008

Intel Adds Some Detail to Their Roadmap

by Michael Feldman, HPCwire Editor

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On Monday, Pat Gelsinger, Intel's senior vice president and general manager of the Digital Enterprise Group previewed the press and analysts about the upcoming processor changes that Intel will be rolling out over the next couple of years. The main topics included Tukwila, Dunnington, Nehalem, "Visual Computing" and Larrabee. More details and maybe a bit of hyperbole are sure to follow at the Intel Developer Forum (IDF) in a couple of weeks.

Gelsinger spoke only briefly about Tukwila, the quad-core Itanium chip scheduled to be introduced late this year. The new processor sports 30 MB of total cache, the new QuickPath Interconnect (QPI), and dual integrated memory controllers. Intel claims the new chip will double the performance of the current Itanium 9100 generation. Although SGI, and to a lesser extent HP and NEC, use the Itanium for traditional HPC, the chip is now mainly being aimed at mission-critical applications. Gelsinger noted that the Itanium-based servers are continuing to displace into Sparc- and POWER-based machines.

The remainder of the briefing focused on Intel's x86 product lines.

Dunnington, a six-core Xeon processor scheduled to be delivered in the second half of the year, is the 45nm follow-on for the quad-core Tigerton. Like its predecessor, Dunnington is for multiprocessor systems -- i.e., four processors and above -- and is socket compatible with the Caneland platform. According to Gelsinger, the hexa-core configuration represented a tradeoff between cost and performance, with designers deciding that six cores and a large L3 cache (16 MB) struck the right balance.

The most significant processors Intel plans to introduce this year will be Nehalem, a new architecture that will usher in integrated memory controllers (IMCs) and the QuickPath Interconnect into the x86 family. The new design allows Intel to jettison the antiquated Northbridge chip and associated front-side bus. Each CPU supports two QPI links per socket, with each link providing up to 25.6 GB/sec of bandwidth. Nehalem will bring Intel in line with AMD, architecturally speaking, and for the first time should allow Xeon processors to achieve the level of scalability and memory performance associated with their Opteron counterparts.

In Nehalem, the on-chip DDR3 memory controller supports up to three DIMMs per channel on each processor. According to Intel, the new setup will provide four times the memory bandwidth and about half the memory latency as the current Penryn chips. "The bandwidth coming out of this is truly stunning," said Gelsinger. "...Some of our most performance sensitive customers are going to see fabulous results."

Nehalem processors will contain between 2 and 8 cores and be modular in design. The idea is to mix and match silicon building blocks (x86 cores, cache, IMCs, QPI and integrated graphics), which gives Intel more flexibility in assembling different chip configurations for different markets. Nehalem also adds simultaneous multithreading (2 threads per core), includes shared level 3 cache, adds dynamic power management, and incorporates SSE upgrades. Under the hood, the hardware designers have increased the micro-ops in flight by 33 percent, enhanced cache algorithms for faster unaligned accesses, sped up the synchronization primitives, enhanced branch prediction, and added a two-level TLB hierarchy.

Taking all the new features into account, Nehalem probably represents the largest architectural change the company has ever undertaken with its x86 line. The first Nehalem product -- a quad-core processor -- is scheduled to be delivered by the end of this year. In 2009, Gelsinger said we will see versions with integrated graphics, higher core counts, and different memory configurations.

In late 2009, the company plans to introduce Westmere, the 32nm shrink of Nehalem. In 2010, the new Sandy Bridge architecture will be introduced on the 32nm node. Sandy Bridge will include Advanced Vector Extension (AVX), a 256-bit vector extension to SSE for FP-intensive applications. By doubling the vector width from the current 128-bit SSE implementation, Intel claims AVX should increase peak floating point performance by a factor of two. Better data primitives allow operations such as sparse matrix computations to be accomplished more easily. In addition, three operand non-destructive instruction syntax has been added to simplify code generation and provide more opportunities for parallel loads and computes for the compiler. The new instructions are aimed at revving up multimedia processing and high performance technical computing applications. Gelsinger characterized the AVX technology as "SSE on steroids."

Even before Sandy Bridge becomes a reality, Intel plans to roll out Larrabee, the company's much-talked about discrete graphics processor family. The manycore architecture will scale to teraflops and beyond -- not too much of a stretch when you consider current high-end GPUs from AMD and NVIDIA already achieve half a teraflop (single precession). The first Larrabee demos are planned for later this year, with products showing up in 2009 or 2010.

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