HPCwire: Finding the Door in the Memory Wall, Part 1

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March 03, 2009

Finding the Door in the Memory Wall, Part 1

by Erik Hagersten, CTO of Acumem

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Multicore processors are here, and new articles and products are targeting the need to parallelize applications. There are three common misunderstandings about parallel processing discussed in this article: (1) Embarrassingly parallel execution will always benefit from multicore architectures; (2) The memory wall is a hardware-only showstopper for performance; (3) Going green only implies investing in power-efficient hardware.

Many HPC applications, sequential or parallel, often treat the shared resources of a multicore processor in a wasteful way and unnecessarily crash into the memory wall at high speeds. This may lead to superlinear slowdown, even for embarrassingly parallel applications. Often, simple rewrites of the applications can avoid the memory wall, or at least move it further away. Thus, we cannot blame hitting the memory wall on hardware alone. Usually, some alteration to software is possible to avoid the bottleneck. Making the software more efficient may be the simplest and least expensive way to save power and resources.

HPC Computer Landscape of 2009

A multicore architecture replicates some hardware resources, typically the pipelines and the L1 caches; while other resources are not replicated and are shared by the many active threads running on the processor. Examples of such shared resources are the shared cache (L2 and/or L3) and the DRAM bandwidth. But if increasing the number of cores in the future will increase the peak FLOPS and MIPS, what will happen to the shared resources?

As pointed out in HPCwire by Michael Feldman, we cannot expect any new major improvement in memory bandwidth beyond DDR3 at any time soon. This is likely to be an Achilles heel for future multicore processors. Studying the improvement of cache capacity per active thread does not make the picture any prettier. Looking back, the HPC servers of the 90s often had several megabytes of last-level cache per CPU. Since each CPU executed only one thread, that was also equal to the cache capacity per thread. A multiprocessor system (e.g., SMP) built from many such CPU chips, grew the total cache capacity linearly with the number of threads (i.e., CPUs, a.k.a. cores). Sometimes this even resulted in superlinear speedups, since more active threads also implied more total cache capacity for the parallel application.

Typically, each new and faster generation of CPUs in the 1990s came with larger caches. A rule of thumb for us architects at Sun Microsystems back then -- building servers based on UltraSPARC I and II -- was that doubling the cache capacity yields roughly 50 percent performance improvement for important applications. Of course, that is not an absolute truth but may say something about the state of mind of large-scale server designers in the previous decade.

In a multicore design, cache capacity is shared among all the cores, where each core is possibly running several threads simultaneously. The new Nehalem processor, for example, has four cores, each one running two threads, sharing 8 megabytes of cache. Cache capacity per thread in 2009 (1 megabyte) is lower than what we grew used to in the 1990s, and the total cache capacity does not scale with the number of cores, as was the case for the SMPs back then. This is likely to make the memory wall higher, rather than lower, in the future.

Embarrassingly Parallel Execution and Superlinear Slowdown

One example of embarrassingly parallel execution is that of throughput computing, where several independent applications are running on a server. Most supercomputers today do exactly this, that is, many single-threaded applications are executed simultaneously and perform completely their tasks independently. This embarrassingly parallel workload may appear to be ideal for multicore processors, but it can actually result in devastating performance, as demonstrated by this graph:

The graph shows the amount of useful work performed by a multicore chip running a throughput workload, in this example, instances of a Lattice Boltzmann Method application, similar to the one used in SPEC2006. While going from one to two cores does indeed result in a throughput improvement of about 50 percent, there is actually performance degradation when going from two to three cores, which we jokingly refer to as a superlinear slowdown.

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