HPCwire

The Leading Source for Global News and Information Covering the Ecosystem of High Productivity Computing

HPCwire >> Features

Intel Gets Ready to Push Ct Out of the Lab


With the advent of general-purpose GPUs, the Cell BE processor, and the upcoming Larrabee chip from Intel, data parallel computing has become the hot new supermodel in HPC. And even though NVIDIA took the lead in this area with its CUDA language environment, Intel has been busy working on Ct, its own data parallel computing environment for manycore computing. On Wednesday at the Intel Developer Forum in Beijing, Senior Vice President Pat Gelsinger announced that the company's Ct research project is on its way to becoming a product, with a beta release scheduled for late this year.

Ct (C/C++ for throughput computing) is a high-level software environment that supports data parallelism in current multicore and future manycore architectures. According to James Reinders, whom I spoke with prior to Gelsinger's announcement, Ct allows scientists and mathematicians to construct algorithms in familiar-looking algebraic notation. Best of all, the programmer does not need to be concerned with mapping data structures and operations onto cores or vector units; Ct's high level of abstraction performs the mappings transparently. The technology also provides determinism so as to avoid races and deadlocks.

"The two big challenges in parallel computing are getting it correct and getting it to scale, and Ct directly takes aim at both," said Reinders.

Unlike CUDA, Brook+, or OpenCL, Ct provides a more high-level approach to data parallel processing, where vectors may be represented as regular or irregular data collections. This enables the programmer to define sparse matrices, trees, graphs, or sets of value-key associations, as well as the more typical dense matrices. The language is implemented as an extension to C++ using the standard template facility, so legacy code can be expanded to include data parallelism by using new Ct data types and operators.

Intel will be adding Ct to its growing portfolio of parallel development tools, including the upcoming Parallel Studio suite, the company's C/C++ and Fortran compilers, Math Kernel Library, debugging and analysis tools, and the Intel Cluster Toolkit. Ct will also be interoperable with Threading Building Blocks (TBB) and Intel's OpenMP implementation so that task-level parallelism can be layered on top of Ct's data parallelism. "Our vision is that you could have TBB coordinating multiple tasks and those tasks could be coded using Ct," explained Reinders.

Although Ct is intrinsically target-agnostic, it does assume a general-purpose CPU-ish architecture with enough vector hardware to make data parallel computing worthwhile. Ct will, however, not support strictly SIMD architectures like NVIDIA and AMD GPUs. Initially this means the first Ct implementation will target x86 multicore chips with Streaming SIMD Extensions (SSE) capability. Conveniently, this includes support for AMD x86 silicon too. All of Intel's current set of compilers and libraries support AMD processors, and Ct will be no different. Unlike the hardware side of the business, Intel's software customers expect x86 compatibility across company lines.

The broader plan for Ct is to provide a platform that allows developers to seamlessly move their software from today's multicore chips to future manycore processors. So an application written for a quad-core Nehalem processor with SSE4 will transparently scale to an eight-core Sandy Bridge chip with Advanced Vector Extensions (AVX), and eventually to a Larrabee processor with its own native vector instruction set.

Beyond x86 support, the long-range vision for Ct is to be able to apply the technology across a range of architectures. Again, Intel the chipmaker is not interested in this as much as Intel the software maker, whose customers are more focused on industry standards rather than pledging allegiance to specific silicon.

Reinders is not quite sure how multi-architecture support will play out. Placing Ct into the open source realm, providing APIs into the code, and initiating direct engagements with interested parties are three possibilities. Alternatively, Ct could be engineered to sit on top of a low-level interface to DirectX or OpenCL, which would provide its own avenue to target independence.

Underlying all this is the customer demand for a parallel programming environment with enough staying power to bridge the multicore-to-manycore transition. There are a plethora of parallel programming products out there today -- CUDA, RapidMind, Cilk++, UPC, and so on -- but customers want to make sure that their software doesn't have to be continually re-coded to new environments. People are just starting to deploy parallel applications on multicore architectures today and are already worried that their current software model isn't going to survive the trip to manycore.

But even the Ct story gets a little murky when you start talking about manycore. Larrabee, Intel's first x86 manycore architecture, which coincidentally provides a lot of data parallel capability, is not the principle target of Ct -- at least not yet. As we reported last year, the first implemention of Larrabee will be targeted to graphics and visual computing applications, not the more general-purpose technical computing applications (seismic analysis, financial analytics, scientific research, high-end imaging, etc.) that Ct is aimed at.

The contradiction here is that Larrabee has demonstrated (at least in simulated tests by Intel) almost perfect scaling across a range of Ct-enabled data parallel apps. No doubt this is due to the architecture's strength in vector processing, where each core includes a 512-bit vector processing unit that can process 16 single-precision floating point numbers at a time. But since the first Larrabee products will have the same limitations for general-purpose computing as a traditional GPU, the initial offerings are not slated for HPC duty.

On the other hand, Reinders certainly expects HPC enthusiasts will want to experiment with Larrabee and will be interested in using Ct as the software platform for such work. At this point though, Intel hasn't decided how much Larrabee support will end up in the initial version of Ct. "I think you can expect to see an answer to that by the end of the year, as Larrabee is coming available," said Reinders.


HPCwire on Twitter

Article Tools

  • Print This Page
  • Bookmark This Article

Share Options

(Digg, Technorati, more)


Subscribe

Discussion

There are 0 discussion items posted.  

HPC in the Cloud Part 2
People to Watch 2010


Top Headlines

Intel Partners See 'Easy' Upgrade Path With Xeon 5600 Chips

Mar 18 | ChannelWeb | Westmere parts already showing up in HPC machines. Read more...

AMD: OEMs primed for Opteron 6100s

Mar 17 | The Register | But what about the tier ones? Read more...

Arrival of the Desktop Supercomputer

Mar 17 | Cadalyst Magazine | A new generation of workstations is changing the nature of technical computing. Read more...

Scheduling HPC In The Cloud

Mar 17 | Linux Magazine | Latest iteration of Sun Grid Engine able to tap into Cloud. Read more...

Tailoring Medicine with Supercomputers

Mar 16 | Bio-IT World | Biotech firm builds genetic models from patient data. Read more...

Featured Whitepapers

Virtualization for Aggregation And The vSMP Architecture™

Jan 12 | | In-depth look at vSMP Foundation server virtualization technology, technical implementation, use cases and capabilities. The technical whitepaper provides an architectural overview and details on the three vSMP Foundation products: vSMP Foundation for SMP, vSMP Foundation for Cluster and vSMP Foundation for Cloud.

Copper Cable Technologies for High Performance Computing

Jan 18 | | This white paper discusses Gore’s copper cable assemblies, and how they continue to exceed the standards for providing reliable, cost-effective solutions for high-performance computer applications.

Multimedia

Webcast: Virtualized Data Center Roundtable

Join this online panel discussion for live Q&A with leading industry experts, analysts, and end-users to discuss the latest innovations, best practices, barriers to implementation, and measurable benefits of server virtualization with a particular focus on today's real world solutions.

Webcast: Watch SC09 Birds of a Feather Video: Scalable Fault-Tolerant HPC Supercomputers

Learn about scalable fault-tolerant architectures and examples of energy efficient and scalable supercomputing clusters using dual QDR InfiniBand to combine capacity computing with network failover capabilities with the help of programming languages such as MPI and a robust Linux cluster management package.

Webcast: High Performance Computing for a Smarter Planet

LIVE@SCO9: The IBM team discusses new innovations in hardware, software and services that help clients better understand their workloads and get insight from their R&D efforts. Technology demonstrations include the soon-to-be-released Power7 HPC processor, the DCS990 system with 2.4 petabytes of storage, the xCAT management tool, secure HPC cloud computing and more. Winners of two HPCwire Readers' and Editors’ Choice Awards! Take the IBM virtual tour at SC09 or more information go online to: http://www-03.ibm.com/systems/deepcomputing/sc09.html

SC09 HPC in the Cloud

Newsletters

Stay informed! Subscribe to HPCwire email Newsletters.






HPC Job Bank


Featured Events

HPC User Forum DICE
2010 High Performance Computing Linux Financial Markets
Cloud Computing Expo
Cloud Lab
ESC
DEISA PRACE Symposium