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May 04, 2007
The Uncommodity Solution
The current obsession with energy-efficient FLOPS in high performance computing systems has created a diversity of solutions in the last few years. The Cell processor and GPUs have been getting a lot of attention from the media, including yours truly. By offering hundreds of gigaflops at Wal-Mart prices, vendors and do-it-yourself HPC users are being tempted to experiment with these latest commodity accelerators.
With this as a backdrop, ClearSpeed has the unenviable task of offering floating point accelerators at $8000 a pop. Since high performance computing is the only market to which they aspire, the company lives in the relative anonymity of the HPC world. Not having the market breadth or sexiness of Cell processors, GPUs or FPGAs, ClearSpeed coprocessors are promoted on their technical prowess. If this were "Survivor," ClearSpeed would have been kicked off the island a year ago. Fortunately this is reality IT, not reality TV.
Since the company was unveiling its new PCI Express-capable Advance board this week, along with some SDK and math library upgrades, I took the opportunity to get an update about the company's strategy to compete in a commodity-dominated industry. If you want to know more about ClearSpeed's new offerings, read their press release in this issue.
ClearSpeed does have an interesting tale to tell. One of the advantages of not being a commodity solution is not having to worry about consumer applications like PlayStations or PCs. ClearSpeed designs its coprocessors specifically for floating point speed and energy efficiency. In doing so, the company maintains it has the best performance/watt in the industry and it intends to keep that lead indefinitely.
What ClearSpeed offers today is a dual-coprocessor Advance board that tops out at 55 gigaflops (using a double-precision matrix multiplication benchmark). Each 10-watt CSX600 coprocessor provides 27.5 gigaflops, yielding 2.75 gigaflops/watt.
Compared to their commodity brethren, this might not seem like such a great feat. The latest NVIDIA GeForce 8800 GTX achieves 518.4 Gigaflops with 177 watts, yielding 2.93 gigaflops/watt. But the gigaflops in this case are single-precision FLOPS and are calculated for shader processing. Since there is no double-precision GPU on the market today (NVIDIA says it intends to offer one later this year), the comparison with the ClearSpeed offering is not yet relevant. AMD also has also not yet released a double-precision GPU product.
The Cell processor has a double-precision capability, but it's only a tenth or so of its single-precision performance. IBM is promising a much more capable double-precision version soon. Even the current version of the Cell processor provides a respectable 14.6 gigaflops of double-precision matrix multiplication with just 80 watts. This yields 0.18 gigaflops/watt, but that's less than a tenth of the performance of ClearSpeed's hardware.
FPGAs are another possibility for floating point. In general though, there's not enough real estate on the current implementations to allow for a lot of double-precision logic. At the present level of technology, you can squeeze between five to fifteen gigaflops on a single chip. But laying out the circuits to even do this requires a good deal of FPGA programming smarts. That doesn't keep HPC enthusiasts from trying though.
The fact that the CSX600 coprocessor is built on a 130nm process technology, while the GPUs, Cell chips, and the majority of FPGAs are built on 90nm, attests to ClearSpeed's skill in churning out the FLOPS with a relatively slow clock. The CSX600 contains 96 processing cores, which run at a rather modest 210 MHz.
Another advantage of the ClearSpeed coprocessors is accuracy. While no commercial FP device is fully "conformant" to the IEEE 754 floating point specification, ClearSpeed is compliant with the rounding conventions. On the other hand, while the Cell and GPUs are compatible with IEEE 754 floating point numerical formats, they don't do 754-type rounding. Values are just truncated in the hardware.
"When you think about their [GPUs and Cell processors] design criteria, which is to put pixels on a screen, whether it's for a Sony PlayStation or for graphics on a computer, it was certainly sufficient," explained Peter ffoulkes, ClearSpeed's Director of Outbound Marketing. "But it's not sufficient when you're looking at some of the math applications, particularly for double-precision and high accuracy types of applications. When Cell and GPUs go to 64 bits, they may well chose to implement more of the IEEE 754 specification."
"Even if they do implement everything properly, we feel that we're going to have a substantial advantage in performance/watt," ffoulkes added. "They won't be able to get anywhere near [us]."
Hooking coprocessors into standard x86 servers can yield an interesting type of efficiency. ClearSpeed points out that by adding floating point horsepower in a server using a single Advance board, they were able to demonstrate a power reduction in the x86 component that made up for a significant chunk of the board's power consumption. In essence they were able to realize an extra 34 gigaflops of performance with just 6 additional watts of power compared to the base system -- in this case an HP server with dual-core Xeon processors. Presumably this happened because the the Xeons could run a lot cooler once relieved of their floating point duties.
The company calls this the "Top Up" perspective, which sounds like a marketing ploy, but it does point to an extra efficiency that can be gained from accelerator add-ons. It's comparable to the sort of synergy you get with gas-electric hybrid cars, where the electric component improves the efficiency of the gas engine. After spending close to $50 to put 12 gallons into my car, I kind of wish ClearSpeed would start designing automobiles. High performance ones of course.
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As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at editor@hpcwire.com.
Posted by Michael Feldman - May 4 @ 12:00AM
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Michael Feldman
Michael Feldman is the editor of HPCwire.
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