HPCwire: HyperTransport 3.0 Specification Released

The Leading Source for Global News and Information Covering the Ecosystem of High Productivity Computing

Leading HPC
Solution Providers

HPCwire >> Off the Wire

April 28, 2006

HyperTransport 3.0 Specification Released

HyperTransport Technology Consortium, a standards organization dedicated to developing the industry's lowest latency, highest bandwidth interconnect technology, has released version 3.0 of the HyperTransport specification. The new standard nearly doubles the bandwidth and speed of the previous HyperTransport 2.0 specification. In addition, HyperTransport 3.0 supports a variety of new features including AC coupling mode, hot plugging, un-ganging mode and dynamic power management for the support of extended signal transmission distance, typical of backplane and chassis-to-chassis implementations. HyperTransport 3.0 builds on the existing HyperTransport 1.0 and 2.0 standards which continue to be designed into systems at an accelerating rate, and have helped HyperTransport reach considerable market presence and success. HyperTransport 3.0 is fully backwards-compatible with earlier versions of the HyperTransport specification standard.

"The added performance and new features of HyperTransport 3.0 extend the applicability of HyperTransport technology from chip-to-chip and board-to-board, all the way to chassis-to-chassis applications," said Mario Cavalli, general manager of the HyperTransport Technology Consortium. "HyperTransport has proven to be the industry's most flexible, powerful and future-ready standard interconnect solution for compute-intensive system designs, delivering a winning combination of high-performance, standardization and optimized total cost of ownership for data center and supercomputing applications."

There are over 40 million HyperTransport technology-enabled systems in perhaps the industry's widest range of applications for interconnect technologies. HyperTransport technology is deployed in applications ranging from high-performance embedded systems to personal computing, workstations, servers, supercomputers and clusters.

HyperTransport 3.0 extends the 1.4 GHz dual data rate (DDR) maximum clock of HyperTransport 2.0 to 1.8 GHz, 2.0 GHz, 2.4 GHz and 2.6 GHz, and delivers a maximum aggregate bandwidth of 41.6 gigabytes per second (GB/s) -- a bandwidth increase of 86 percent over HyperTransport 2.0.

"As processor performance continues to rise, and the industry increasingly moves toward a new generation of multi-core technology, multi-CPU system designs, interconnect latency and bandwidth take on a pivotal role in overall system and application performance," said David Rich, president of the HyperTransport Consortium. "By further reinforcing HyperTransport's industry position as the lowest latency, highest bandwidth interconnect technology, HyperTransport 3.0 enables designers to achieve state-of-the-art application performance and optimum time-to-market advantages while benefiting from the combined economies of scale of a widely adopted interconnect standard and a full array of off-the-shelf systems and components."

Technical Features and Benefits of HyperTransport 3.0

-- AC mode (Optional) - An innovative AC interconnect mode complements HyperTransport's traditional DC mode, featuring capacitor coupling, AC/DC auto-sensing and auto-configuring capabilities. The feature extends HyperTransport's maximum signal transmission distance to 1 meter at maximum specified clock speed with no signal transmission or performance degradation. As a result, the HyperTransport standard can now support long-haul signal transmission typical of backplane and chassis-to-chassis applications. During power-up and in total transparency to system software, HyperTransport 3.0 auto-senses the presence of coupling capacitors (AC) and/or direct connections (DC) within the HyperTransport interconnect fabric and automatically configures each portion of it accordingly.

-- Hot plugging - HyperTransport technology-enabled devices can be added to or removed from the HyperTransport fabric without disrupting system operations. HyperTransport cards, systems and subsystems can therefore be deployed in backplane and mission-critical platforms requiring high system availability.

-- Un-ganging mode (Optional) - During system power-up and transparently to system software, 1x16 HyperTransport links can optionally be configured as 2x8 virtual links. This gives system architects extended interconnect flexibility and the ability to fully leverage existing HyperTransport components and cores. Un-ganging mode is particularly valuable in multiprocessor and symmetric multiprocessing environments.

-- Power Management Mode - HyperTransport 3.0 carries dynamic, auto-sensing, hardware-based, self-configuring power management capabilities that give end products the intelligence to best optimize the power consumption of each of their HyperTransport components and modules in real-time and transparently to operating system (OS) and application software.

"Today's announcement is not only a celebration of HyperTransport technology's increasing adoption across a broad spectrum of commercial and consumer markets, but also enables AMD to continue to expand its position as an industry leader," said Randy Allen, corporate vice president, Server and Workstation Division, AMD. "When AMD originally developed HyperTransport technology, it was with the goal of enabling the most scalable, high performance systems for enterprise computing. The flexibility and scalability that HyperTransport provides not only allows AMD to provide the best performing solutions in the industry, but when combined with inherently power-efficient processor architectures, such as the AMD Opteron processor, allows for industry leading performance per watt, as well."

"Cray has a long-standing history of designing and delivering supercomputers with superior interconnects," said Steve Scott, Chief Technology Officer of Cray Inc. "HyperTransport technology provides an ultra low latency, high bandwidth connection directly from the processor's memory system to our high speed network. We've integrated it into two of our current product lines, the Cray XT3 and Cray XD1 systems. Together with our strategic partner, AMD, we expect to continue this practice in future product generations."

"As a leading supplier of current generation HyperTransport link layer cores, GDA Technologies is committed to helping its customers in computing and networking markets adopt the latest in high speed interconnect technology," said AG Karunakaran "AGK", president of GDA Technologies, Inc. "We are proud to be one of the first IP and service providers to provide synthesizable link layer cores utilizing the new HyperTransport 3.0 and providing support for different HyperTransport configurations."

Article Tools

Share & Save Options

Discussion

There are 0 discussion items posted.

Join the Discussion

You must be a registered user in order to comment on HPCWire stories.

Members enjoy:

	Access to Special Content, including Podcasts, Webcasts, and Whitepapers and more!
	Ability to take an active role in the discussions that are shaping the HPC technology discipline!
	Special offers available only to HPCWire members!

Become a Registered User Today!

Registered Users Log in Here to Comment

Email Address:	Password (case sensitive)

Remember me	Forgot Password?

RSS Feeds

Feeds by Topic

Feeds by Industry

Feeds by Content Type

Feature Articles

'Coopetition' Helps the UK HPC Market Go 'Round

The size and diversity of the HPC market in the United States supports a varied set of system providers and integrators. But in Europe, and the United Kingdom in particular, the market has a different shape.
Read More...

The Week in Review

PRACE to evaluate petaflops prototypes; Acadamic roundtable discusses the computing industry's talent pool; and WRF benchmark data are released. John West recaps those stories and more in our weekly wrap-up.
Read More...

Semantic Supercomputing Reaps Competitive Advantage from Patent Data

Since the first patent was issued for a Venetian statue in 1471, 60 million patents have been awarded around the world, with four million patents actively in force today worldwide. And 800,000 new inventions are registered every year. While the data is public, current search tools are inconvenient and inadequate to the needs of professionals. Semantic supercomputing techniques are helping researchers tackle this difficult challenge.
Read More...

Read more HPCwire features...

Top Headlines

25 Years of Conventional Evaluation of Data Analysis Proves Worthless In Practice

Sep 05 | Uppsala University | Swedish researchers are revealing that "intelligent" computer-based methods for classifying patient samples is worthless when it comes to practical problems. Read more...

Three Dimensional Scans Could Revolutionise Brain Surgery

Sep 03 | Telegraph.co.uk | A new form of three dimensional scans could revolutionise brain surgery within a year, doctors claim. Read more...

Marching Penguins: Monitoring Your HPC Cluster

Sep 03 | Linux Magazine | In HPC, most attention is paid to utilization and performance, rather than service availability and problem notification. This article focuses on the latter Read more...

Big Data: Welcome to the Petacentre

Sep 03 | Nature News | What does it take to store bytes by the tens of thousands of trillions? Read more...

UD Scientist Finds Quicker Computer On-Ramp

Sep 01 | Delaware Online | In the world of supercomputer-powered science, speed is everything, and an open road can lead to the promised land. Read more...

Read more headlines...

Featured Whitepapers

SUSE® Linux Enterprise Server for High Performance Computing

Sep 05 | | The excellent scalability features of Linux, in addition to robust security and performance makes it an excellent choice for server systems, especially in the high performance computing area.

“Going Parallel - An Implementation Guide”

Sep 01 | | The paper outlines the basic steps and tools involved in the process of migrating a desktop application to a parallel environment.

Improving Performance and Manageability for Seismic Processing and Imaging Applications with Parallel Storage

Jun 05 | | As pressure increases on the upstream seismic processing community to deliver ever-higher levels of productivity and efficiency, a new generation of storage solutions will be required that allow the maximum utilisation of high-performance computing (HPC) Linux cluster resources, together with the minimum of management overhead.

View the White Paper Library

Multimedia

Video White Paper: Architecting a Better Network Storage Solution

BlueArc's Titan architecture represents an evolutionary step in file servers by creating a hardware-based file system that can scale bandwidth, IOPS, and overall data capacity well beyond conventional software-based devices. With its ability to virtualize a massive storage pool of up to four usable petabytes of tiered storage, Titan can scale with growing data requirements, offering a competitive advantage for businesses, researchers, or other enterprises seeking to better manage data growth while still ensuring optimal performance.

Podcast: Interview with Ben Bennett of ClearSpeed Technology

Today, HPC organizations are requiring substantially more floating point performance to solve real-world problems. In this podcast, Ben Bennett, ClearSpeed General Manager, discusses how acceleration technology can improve the overall performance of standard x86-based systems...