NCSA
HPCwire

Since 1986 - Covering the Fastest Computers
in the World and the People Who Run Them

Language Flags

Visit additional Tabor Communication Publications

Datanami
Digital Manufacturing Report
HPC in the Cloud
Green Computing Report

Tabor Communications
Corporate Video

Why Pretend?


InfiniBand and iWARP have industry heavyweights behind them, to be sure. But this kind of smug satisfaction has only led to a case of the Emperor's New Clothes in which no one is willing to admit to the inadequacy of RDMA in general and VIA in particular.

Kernel Bypass, Zero Copy, and Asynchronous Communication

Networks are a shared resource. Traditional networks such as Ethernet require that the resource be protected by the kernel, which presents a tremendous performance bottleneck when latency is an issue. Furthermore, data is copied to and from pre-allocated buffers, which can hurt bandwidth for large messages.

Many of today's high-performance networks from vendors such as Myricom and Quadrics handle the protection across process boundaries directly through the network interface card (NIC). This setup bypasses the kernel and lets communication occur at the user level, thereby removing the bottleneck of mode switching.

Most modern high-performance networks also have direct memory access (DMA) in which the NIC accesses main memory directly while the CPU is free to perform other tasks. DMA not only eliminates copying, but also permits communication to overlap with computation. This facet is similar to prefetching in the cache as it reduces the effective latency. Taking advantage of this feature in an application only requires asynchronous communication, which is represented as multithreaded designs in Sockets or as nonblocking primitives in MPI -- MPI_Isend() and MPI_Irecv().

Send/Receive and RDMA

Most of the above capabilities are available through the widely-used two-sided semantics of Send/Receive communication. That is, the communication runs entirely at the user level, allows the local (sending) node to act without copying, and frees the CPU to perform other tasks. Send/Receive does have a drawback though: the remote (receiving) node must copy the message to its final destination; the benefit of zero-copy only exists for the sending node.

With one-sided semantics in remote direct memory access (RDMA), the receiving NIC uses DMA to place the data into a buffer that has been specified by the sending node. RDMA extends zero-copy benefits to the remote node.

For the NIC to access the data through RDMA, the user's page must actually be in memory and not on the disk. Pinning the page to physical memory requires a memory registration, which invokes the operating system. This is actually an expensive procedure as it requires the kernel and is exactly what high-performance networks are supposed to avoid!

Furthermore, the sending node must know the destination memory address on the receiving node. Most applications, such as those written in Sockets or MPI, will require that this information be exchanged prior to communication. The synchronization here is performed through the Send/Receive semantics in a rendezvous protocol, which adds even more overhead.

Workarounds for RDMA

It is possible to overcome RDMA's shortcomings and still realize the benefit of zero-copy communication on the remote node. Certain supercomputers such as the Blue Gene rely on a custom lightweight kernel that only runs one process; because there is no paging, there is no requirement for memory registration.

Alternatively, QsNet works by patching the kernel so that the NIC may access the appropriate data once the page has been loaded into memory. Patches are developed for very specific versions of the kernel based on assumptions regarding the Linux API. Given this level of required specificity, administering a cluster that involves kernel patches can be quite tedious.

As for InfiniBand, it is possible to rely on caching techniques. That is, if a certain memory region will be remotely accessed multiple times, then the software -- an implementation of MPI, for example -- may build a table of memory registrations on the receiving node.

In any case, synchronization remains unavoidable in most programs. The sending node must know the destination memory address on the remote node to perform RDMA. There are some special cases where the address will be known ahead of time, as in MPI-2's remote memory access functions -- MPI_Put() and MPI_Get(). But these routines are not widely used and represent a niche application.

Specific Issues with the Virtual Interface Architecture (VIA)

MVAPICH is a port of MPICH to InfiniBand maintained by D. K. Panda's team at Ohio State University. This implementation provides a reference for other communication layers on VIA-based networks, such as InfiniBand and iWARP. Of particular interest is that OSU's collection of related research papers contain a series of design patterns for software on RDMA networks.

Design patterns are best-practice architecture that permit reuse of a solution to a common programming problem. Some language researchers, such as Paul Graham and Peter Norvig, believe that design patterns are really a sign that the underlying language is incomplete. After all, a pattern implies automation, and automation implies a machine.

By extension, the design patterns from OSU demonstrate that InfiniBand lacks the foundations that would best serve most of its users. Now some designers, such as John Hennessy and David Patterson, believe that an architecture should provide primitives and not solutions. But given that the (committee-defined) InfiniBand standard is over a thousand pages long, it should be fairly obvious which view the IB Trade Association holds.

In contrast, both the Elan and MX libraries (for QsNet and Myrinet, respectively) have been specifically built to present the common functionality required in most applications. The solutions-oriented VIA community should have done the same with their libraries, such DAPL and the OpenFabrics verbs API.

Personal Notes

I was motivated to write this article after reading "A Tutorial of the RDMA Model" from IBM's Renato Recio, which in turn was a response to "A Critique of RDMA" from Myricom's Patrick Geoffray. I got the impression that Recio was writing to protect the image of VIA rather than provide a sound rebuttal to Geoffray's technical arguments about RDMA. For example, Geoffray's criticism that RDMA is not adequate for Sockets is met with the response that the user can rely on Extended Sockets or the Sockets Direct Protocol (SDP). Extended Sockets is a different library from Sockets, albeit somewhat similar; SDP is a protocol used above and beyond the RDMA paradigm. Geoffray essentially said that RDMA is handicapped and Recio responded that RDMA has a choice of crutches.

What is particularly telling is that Recio fell back on the old technique of using sales volume to justify technical soundness. He states, "it is interesting to note that almost twice as many new machines in the top100 are using InfiniBand than Myrinet." This is like saying that Titanic was the best movie ever produced since it sold the most tickets. If IBM really did believe the sales-volume pitch, it would stop making POWER chips and simply bundle x86 with its servers.

I wrote this article as a knowledgeable end user; I will leave the marketing brochures to the vendors. At Oxford we used to believe that RDMA was a godsend for the BSP-style programming found in MPI-2 or Cray's SHMEM. Indeed, Geoffray's article states that RDMA networks "can be leveraged successfully for one-sided programming paradigms." After having studied both the paradigms and the networks, I have come to the conclusion that models such as the partitioned global address space languages are really best suited for ccNUMA machines. And indeed, that is what RDMA is: a crude approximation of a non-commodity machine useful only for niche applications.

Sockets work just fine on vanilla Ethernet. MPI works on Ethernet. Google's MapReduce works on Ethernet. Maybe this is the architecture we should be building on.

The author would like to thank Richard Brent and Peter Strazdins for their comments on an earlier draft of this article.

-----

Christopher C. Aycock is wrapping up his PhD from Oxford University, where his thesis topic is in communications programming paradigms for high-performance networks. He is currently a visiting fellow at the Australian National University and can be reached via chris@hpcanswers.com.

June 18, 2013

June 17, 2013

June 14, 2013

June 13, 2013

June 12, 2013

June 11, 2013

June 10, 2013

June 07, 2013

June 06, 2013

June 05, 2013


Most Read Features

Most Read Around the Web

Most Read This Just In


Short Takes

Supercomputers: Not Always the Best for Big Data

Jun 18, 2013 | The world's largest supercomputers, like Tianhe-2, are great at traditional, compute-intensive HPC workloads, such as simulating atomic decay or modeling tornados. But data-intensive applications--such as mining big data sets for connections--is a different sort of workload, and runs best on a different sort of computer.
Read more...

Gordon Flashes Its Versatility in HPC Workloads

Jun 18, 2013 | Researchers are finding innovative uses for Gordon, the 285 teraflop supercomputer housed at the San Diego Supercomputer Center (SDSC) that has a unique Flash-based storage system. Since going online, researchers have put the incredibly fast I/O to use on a wide variety of workloads, ranging from chemistry to political science.
Read more...

Supercomputers: Still the King of the HPC Hill

Jun 17, 2013 | The advent of low-power mobile processors and cloud delivery models is changing the economics of computing. But just as an economy car is good at different things than a full size truck, an HPC workload still has certain computing demands that neither the fastest smartphone nor the most elastic cloud cluster can fulfill.
Read more...

TACC Longhorn Takes On Natural Language Processing

Jun 14, 2013 | For all the progress we've made in IT over the last 50 years, there's one area of life that has steadfastly eluded the grasp of computers: understanding human language. Now, researchers at the Texas Advanced Computing Center (TACC) are utilizing a Hadoop cluster on its Longhorn supercomputer to move the state of the art of language processing a little bit further.
Read more...

Titan Didn't Redo LINPACK for June Top 500 List

Jun 13, 2013 | Titan, the Cray XK7 at the Oak Ridge National Lab that debuted last fall as the fastest supercomputer in the world with 17.59 petaflops of sustained computing power, will rely on its previous LINPACK test for the upcoming edition of the Top 500 list.
Read more...

Sponsored Whitepapers

Best Practices in Big Data Storage

05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.

Progress in Parallel: the Bull Parallel Programming Center

04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.

Sponsored Multimedia

HPCwire Live! Atlanta's Big Data Kick Off Week Meets HPC

Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?

Webinar: Mellanox Virtual Modular Switch, the Most Efficient 40GbE Aggregation Switch Solution

Join our webinar to learn how IT managers can migrate to a more resilient, flexible and scalable solution that grows with the data center. Mellanox VMS is future-proof, efficient and brings significant CAPEX and OPEX savings. The VMS is available today.

Atlanta's Big Data Kick Off Week Meets HPC Cray Exxact

HPC Job Bank


Featured Events






  • November 17, 2013 - November 22, 2013
    SC'13
    Denver, CO
    United States


HPCwire Events