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September 21, 2007
It's been said more than once that users of high performance computing have an almost insatiable demand for computational power. Applying Moore's Law to produce additional cores on general-purpose processors helps, but ultimately fails, to keep up with this demand. Bigger systems can be built, but power and size considerations limit scalability.
These obstacles have increased interest in hardware accelerators. FPGAs, GPUs, Cell processors and ClearSpeed boards are all candidates for offloading the kind of fine-grained parallelism common to many HPC applications. Seismic modeling, financial analytics and bioinformatics applications have been sped up anywhere from 10 to 300 times using these newer technologies. And accelerators are able to do this at a fraction of the cost and power of general-purpose CPUs. But in many cases, hyperbole has been delivered faster than real products. For FPGAs, this might be starting to change.
When FPGAs hit the 90nm process node, manufacturers were able to build chips with enough gates and memory on them to host real HPC kernels. The Xilinx Virtex-4 and Altera Stratix II are two such chips. More recently, Xilinx and Altera have delivered even more powerful FPGAs, using 65nm technology -- Virtex-5 and Stratix III, respectively. Reconfigurable computing vendors are just catching up to the newfound treasure. DRC Computer Corp., XtremeData Inc., Celoxica Holdings plc, Nallatech, Mitrionics AB, Impulse Accelerated Technologies and a handful of others are beginning to crack the HPC marketplace.
This week Celoxica announced that its RCHTX acceleration board has been qualified by HP for its ProLiant DL145 server. Customers can now buy an HP server equipped with Celoxica's FPGA board, with HP standing behind it. An accelerated HP machine was demonstrated at the HPC on Wall Street conference on Monday.
The RCHTX board is based on the Xilinx Virtex-4 FPGAs. (Celoxica also has developed support for the next-generation Virtex-5.) According to Jeff Jussel, Celoxica's VP of Marketing, it still can be a challenge to fit some of the algorithms on the 90nm Virtex-4 chips, but there is certainly enough real estate on the die to implement a lot of useful double-precision floating point codes.
"Frankly, we only need to get enough multipliers on the FPGAs to do the job," explains Jussel. "We're finding that they are now big enough so that we can do that."
Celoxica has targeted the financial services space as one sector with an acute need for accelerated solutions and, frankly, one with the wherewithal to invest in emerging technologies like theirs. The company is in the process of carrying out a "paid engagement" for a Tier 1 investment bank to demonstrate a proof of concept for the RCHTX technology applied to the bank's analytics applications. Results of the study have shown improvements in the power-speed ratio of up to 30 times compared to the bank's current server technology.
The partnership with HP is a significant development for Celoxica. Big banks and other financial institutions need to feel comfortable with the level of support they're going to get with their mission-critical technology. With a staff of 46, it's hard for Celoxica to provide that by themselves. They realize hooking up with Tier 1 vendors gives them a big boost into these markets.
One advantage to using FPGAs as an accelerator technology are their reconfigurability. In the financial arena, the same system could be used to do both transaction-level applications, like market data pre-processing, and financial analytics, like options trading and derivative analysis. In Celoxica's current implementation, though, both applications can't be performed simultaneously. The RCHTX card has two FPGAs: user and RTOS. The RTOS FPGA manages the hardware interface and handles the communication between memory, the processors and the user FPGA. The user FPGA is the bigger processor and is completely available for application code. Although the user is limited to running one application at a time, switching codes takes only milliseconds.
Like DRC and XtremeData, Celoxica takes advantage of AMD's Torrenza strategy which opens up the AMD64 platform to third-party coprocessors and allows them to be part of the computing fabric. Celoxica's accelerator card uses a HyperTransport eXpansion (HTX) slot rather than plugging directly into an Opteron socket, but it still benefits from direct connection to the CPU and memory. AMD has positioned Torrenza as a big differentiator against Intel.
"Far from thinking of us as stealing sockets [from them], they're seeing this as a way to steal sockets away from Intel," explains Jussel. "AMD has been a big help as partner. They've tied us in with their server partners and helped support the qualification with people like HP."
Although Celoxica is also part of Intel's Geneseo initiative, which uses PCI Express (PCIe), Jussel says, at this point, HyperTransport is going to be the fastest way to connect to a processor. It gives you native bus speeds and avoids having to negotiate a bridge to an external bus, as would be necessary with a PCIe solution. Intel's answer to HyperTransport, CSI (what Intel is now calling QuickPath), is in the works for 2008 for the company's next-generation Nehalem architecture.
Intel has licensed its FSB technology to Xilinx, Celoxica's partner, so an FPGA-FSB solution is a possibility. But, says Jussel, "It remains to be seen whether or not you can get FPGAs hooked up to it and the motherboards out before [Intel] comes out with CSI."
As a matter of fact, a couple of vendors were able to do just that. At the Intel Developer Conference (IDF) on Tuesday, XtremeData and Nallatech unveiled FPGA acceleration modules that could be plugged into Intel Xeon-based platforms.
At IDF, XtremeData demonstrated their new XD2000i module connected to Intel's FSB. The XD2000i is pin-compatible with the Xeon processor socket in dual- or quad-socket servers. The module will contain three Altera Stratix III FPGAs. Two are reserved for the application. The other one will be used as a bridge to manage FSB communication, allowing the user to reprogram the application FPGAs on the fly.
According to XtremeData, the module was designed to plug into any Xeon DP platform. The company prides itself on fitting into any supported system, by adhering to the CPU vendor's recommended "keep-out space," which allows the FPGA module to fit into anyone's box. XtremeData's module for AMD platforms works the same way, but in this case, via an AMD64 socket. "Anyplace you can fit an AMD Opteron, you can fit our module -- without exception," says Geno Valente, XtremeData's VP of Marketing.
Like Celoxica, XtremeData is heavily focused in the financial service market. Many of their current customers are the big financial institutions, which tend to be shy about talking about their internal technology. But according to Valente, they have about 50 or 60 such customers. Most of them are using the XtremeData modules in Opteron sockets to accelerate Monte Carlo simulations for applications like options pricing.
"It's in the grid, where there are 10,000 CPUs crunching away, playing war games with the bank across the street," says Valente.
The XD2000i solution was made possible because Intel licensed its FSB intellectual property to XtremeData. When you buy the XD2000i module, it comes with the FSB IP in it, but encrypted so that no one else can tinker with it. Intel created a similar arrangement with Nallatech, a Scottish company that specializes in FPGA solutions, who also launched their FPGA-FSB solutions at IDF. Unlike XtremeData's Altera hardware, the Nallatech module is based on Xilinx FPGAs.
The fact that Intel was willing to license the FSB technology suggests that the company realizes that there is value outside of the x86 universe that they can tap into. Intel's Geneseo initiative for PCIe is another example of this line of thinking. The FPGA-FSB solutions give Intel some parity against FPGA-HyperTransport offerings for AMD-based platforms. But the introduction of CSI in 2008 should really level the playing field.
May 23, 2013 |
The study of climate change is one of those scientific problems where it is almost essential to model the entire Earth to attain accurate results and make worthwhile predictions. In an attempt to make climate science more accessible to smaller research facilities, NASA introduced what they call ‘Climate in a Box,’ a system they note acts as a desktop supercomputer.
May 22, 2013 |
At some point in the not-too-distant future, building powerful, miniature computing systems will be considered a hobby for high schoolers, just as robotics or even Lego-building are today. That could be made possible through recent advancements made with the Raspberry Pi computers.
May 16, 2013 |
When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
May 15, 2013 |
Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
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