Visit additional Tabor Communication Publications
September 21, 2007
Humbling experiences are usually instructive. This past summer, my oldest son began his first job out of college at an investment firm. From day one, he was provided a workstation with dual monitors -- something I and most of my colleagues only dream about. An extra monitor today runs only a few hundred dollars, but for most companies, that represents an expense that cannot easily be justified across an entire staff. The lesson here is that financial firms take it for granted that maximizing productivity is a direct way to raise the bottom line. And perhaps more than any other sector, the financial services industry uses technology as a lever to do this.
Maybe that's why the relatively low-profile HPC on Wall Street Conference in New York seems to be attracting more attention with each passing year. The financial sector has quickly become the premier market driver for a lot of high-end computing technology. This past Monday, hundreds of industry attendees listened to sessions about how bleeding-edge hardware and software is being used to change the landscape of market trading and financial analytics.
In a recent conversation I had with Donna Rubin, Sun Microsystems' Director of Worldwide Financial Services, we talked about the changing face of the financial services business.
"What's driving this? The 'electronification' of the market," explained Rubin. "If you go down to NASDAQ and look at how many people are actually on the floor, there are not as many people as there used to be. But that doesn't mean trading isn't happening. Trading is happening in cyberspace, and volumes are increasing phenomenally."
With this year's introduction of Reg NMS, the SEC regulation designed to modernize the National Market System and create a more level playing field for equity traders, the new challenge is to offer deft execution by price, venue and speed. While use of technologies such as InfiniBand, multicore processors, clusters and grid computing in the financial sector is now well-established, more exotic technologies like Cell processors, GPUs and FPGAs are also drawing attention.
FPGAs, in particular, seem to have carved out a niche in this arena. The co-demands of geometrically increasing market data volumes and reduced latency have led to the development of FPGA-equipped appliances that perform real-time pre-processing of market data feeds. Exegy and ACTIV Financial Systems both have market data platforms that use FPGAs to process up to a million or more messages at sub-millisecond latencies.
Once the raw market data is ingested, FGPAs are also being used as accelerators to perform financial analytics for applications like options pricing. Getting the FPGAs as close as possible to the host CPUs ensures the code acceleration is worth the trip. With the advent of AMD's Torrenza strategy and the licensing of coherent HyperTransport, FPGAs can be plugged directly into Opteron sockets. This week at the Intel Developer Forum (IDF), we learned that Intel has licensed its front side bus technology to allow XtremeData and Nallatech to build FPGA plug-ins for Xeon platforms as well. (See our feature article in this week's issue for more coverage of this topic.)
GPUs are getting their share of attention too. At the Wall Street conference, NVIDIA demonstrated a desktop system containing three Tesla GPUs that is capable of evaluating 150,000 options per second. According to NVIDIA, two such systems are capable of evaluating the entire U.S. equity option market in less than a second. In addition, Level-3 Finance used NVIDIA hardware to accelerate a securities pricing application by a factor of 10.
Both FPGAs and GPUs seem to be emerging as viable commodity-based accelerator technologies. Each has its drawbacks, however. FPGAs have suffered from immature programming development tools, while GPUs currently lack some hardware smarts, like 64-bit FP support and error correction for on-chip memory. All of these deficiencies are correctable, especially if customers with deep pockets, like the ones on Wall Street, demand it. But it's not clear if both architectures will survive as application accelerators, since both are being offered to fill very similar roles.
"In my opinion it's really FPGAs versus GPUs. That's the battle," said Geno Valente, XtremeData's VP of Marketing. He believes other accelerator solutions based on ClearSpeed and Cell BE technology will have a tougher go of it. Valente speculates that solutions based on those platforms will have to gather enough customers so that their developers will be able to keep innovating over time.
Maybe. The Cell BE processor seems like a special case. If IBM chooses, it can use its position as a one-vendor ecosystem to drive the Cell into the market. This week the company announced an algorithmic trading platform based on Cell powered blades. At the Wall Street gathering, Dave Turek, IBM's VP of Deep Computing, talked about Cell technology, as well as other IBM solutions like their new enterprise stream computing technology, which we previewed back in June.
Sun Microsystems also has a variety of solutions to throw at Wall Street. The company's focus on energy efficiency and compute density plays well in the power- and space-constrained financial capitals like New York, London and Tokyo. With the exception of the highly multithreaded T1 and T2 SPARC platforms aimed at high-transaction throughput workloads, most of Sun's offerings for the financial sector are more along the lines of the traditional x86-powered InfiniBand clusters. Sun has used key partnerships to penetrate this market. This week Sun, Cisco and Reuters teamed up to deliver a low latency solution for automated and algorithmic trading. No word yet about potential customers.
Intel's Rebuttal to Barcelona
Meanwhile on the left coast, Intel used its IDF meeting in San Francisco to trumpet its upcoming technology and cast AMD's recent quad-core offerings as yesterday's news. Most of the product talk was about Penryn (2007), Nehalem (2008), Larrabee (probably 2009), and the 32nm Westmere generation (2009) -- which I won't go into here.
As reported before, Intel confirmed the first round of the 45nm Penryn family -- the "Harpertown" Xeon processors -- will be introduced on November 12. Benchmark comparisons against AMD processors are already showing up. The Tech Report has not only got hold of some pre-production Harpertown silicon, but also some of the special edition (SE) quad-core Opterons that will presumably be launched in the same time frame. The benchmarks discussed in the Tech Report piece include some CFD, imaging and rendering codes, which should be especially interesting for the HPC crowd.
The results are not particularly inspiring if you're an Opteron fan. The new 3.0 GHz E5472 Xeon pretty much dominated the upcoming 2.5 GHz 2360 SE Opterons in just about every benchmark -- although in some cases, not by much. In general, the Opterons were better in performance per watt, but when measured as energy expended per computational work accomplished, the Xeon E5472 actually came out on top. Where the Opterons really excelled was at idle. But bragging that your hardware is very efficient at not doing anything is not exactly the stuff of killer ad campaigns.
It should be said that the E5472 is probably going to be about twice as expensive as the 2360, so the benchmark comparisons are somewhat bogus. A more comparable chip would probably be the upcoming Xeon E5430, but Tech Report didn't benchmark that one. I think when more apples-to-apples processor matchups are published, the Opterons will look a lot better. But the preliminary results do suggest that AMD will have to kick up their clock speeds if they want to swim with the new Harpertowns.
As I've stated before, AMD's more daunting challenge will be when Intel launches its Nehalem processor family, sometime in the second half of 2008. With the introduction of its HyperTransport-like QuickPath (formerly CSI) system interconnect and integrated memory controller, Intel will have erased AMD's main architectural advantages. Nehalem will also represent the company's foray into modular design, where cores, cache size and I/O can be mixed and matched to create a vast array of processor configurations. According to Intel, the Nehalem design is complete and pre-production wafers are already being fabbed.
The chipmaker also revealed (confirmed really) that Larrabee will indeed be a manycore Intel architecture implementation of a GPU-like processor. I say GPU-like because Intel is not talking about the technology as if it's only intended for mainstream graphics duty. In his keynote speech, Intel CEO Paul Otellini had this to say about Larrabee's mission:
"We think this brings the benefits of Intel architecture in a many-core array to the high-performance, visual-computing segments of the marketplace. We'll deliver teraflops of performance with this chip. And one of the things that we think is a unique advantage is that it will scale easily for software developers. It not only has the code compatibility of everything you're familiar with in IA space, but will have a shared cache to be able to make that an easy programming model for you in the developing community. We think it has applications in supercomputing, in financial services, and physics and health applications. But it's also got one more thing that it's going to be very good at, and that's graphics. And one of the beauties here is that it is not dependent on a new software paradigm. Again, the same existing programming models that you all know today will be applicable to this device as it moves us into discrete graphics."
Something for everyone. In any case, he said they're well into development and hope to have a demo of the product in 2008.
The only real downer to the IDF party was Gordon Moore speculating about the end of his beloved "Moore's Law." He gives it only another 10 or 15 years before it runs up against the fundamental limits of semiconductor physics. On the other hand, Moore left us with some optimistic observations about the nature of "fundamental limits":
"[I]t's amazing to me how the technologists have been able to keep pushing those out ahead of us. About as long as I can remember, the fundamental limits bite us two or three generations out. So far we've been able to get around them."
As always, comments about HPCwire are welcomed and encouraged. Write to me, Michael Feldman, at email@example.com.
Posted by Michael Feldman - September 20, 2007 @ 9:00 PM, Pacific Daylight Time
Michael Feldman is the editor of HPCwire.
No Recent Blog Comments
The Xeon Phi coprocessor might be the new kid on the high performance block, but out of all first-rate kickers of the Intel tires, the Texas Advanced Computing Center (TACC) got the first real jab with its new top ten Stampede system.We talk with the center's Karl Schultz about the challenges of programming for Phi--but more specifically, the optimization...
Although Horst Simon was named Deputy Director of Lawrence Berkeley National Laboratory, he maintains his strong ties to the scientific computing community as an editor of the TOP500 list and as an invited speaker at conferences.
Supercomputing veteran, Bo Ewald, has been neck-deep in bleeding edge system development since his twelve-year stint at Cray Research back in the mid-1980s, which was followed by his tenure at large organizations like SGI and startups, including Scale Eight Corporation and Linux Networx. He has put his weight behind quantum company....
May 16, 2013 |
When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
May 15, 2013 |
Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
May 10, 2013 |
Program provides cash awards up to $10,000 for the best open-source end-user applications deployed on 100G network.
May 09, 2013 |
The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system...
May 08, 2013 |
For engineers looking to leverage high-performance computing, the accessibility of a cloud-based approach is a powerful draw, but there are costs that may not be readily apparent.
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.