Visit additional Tabor Communication Publications
December 21, 2007
EAST FISHKILL, NY, and TOKYO, Dec. 18 -- IBM and Toshiba Corporation today announced that they have entered into a joint development agreement on 32nm bulk complementary metal oxide semiconductor (CMOS) process technology.
Since December 2005, IBM and Toshiba have collaborated on fundamental advanced research related to semiconductor process technologies at the 32nm technology generation and beyond at the research facilities in Yorktown and Albany, New York. Building on the success of this ongoing research collaboration, the two companies have agreed to extend the scope of the joint development work to now include 32nm bulk CMOS process technology.
Under the new agreement, Toshiba joins a six company IBM Alliance for 32nm bulk CMOS process technology development* based in East Fishkill, New York.
Through this collaboration IBM and Toshiba plan to accelerate development of next-generation technology to achieve high-performance, energy-efficient chips at the 32nm process level, and to enhance the companies' leadership in the global semiconductor industry.
"This agreement caps a year of extraordinary momentum for IBM and its semiconductor Alliance Partners," said Gary Patton, vice president for IBM's Semiconductor Research and Development Center. "In 2008 we'll continue to strive to collectively deliver the industry breakthroughs and manufacturing milestones that come from talented engineers and semiconductor experts working in an open, collaborative environment with access to world class R&D facilities such as UAlbany NanoCollege's Albany NanoTech complex."
"This is a promising collaboration," said Mr. Shozo Saito, Corporate Senior Vice President of Toshiba Corporation and President & CEO of Toshiba's Semiconductor Company. "In addition to continuing the successful collaboration on fundamental advanced research, Toshiba will jointly develop the state-of-the-art 32nm bulk CMOS process integration technology, as a member of the world-class seven-company IBM Alliance. Concurrently we will also accelerate our own development of integration technology for the 32nm process at Toshiba's Advanced Microelectronics Center in Yokohama, toward achieving early production of leading-edge devices."
* For recent news on IBM's Semiconductor Alliance partners please see: http://www-03.ibm.com/press/us/en/pressrelease/22858.wss
For further information about IBM Microelectronics, visit http://www.ibm.com/chips/.
The Xeon Phi coprocessor might be the new kid on the high performance block, but out of all first-rate kickers of the Intel tires, the Texas Advanced Computing Center (TACC) got the first real jab with its new top ten Stampede system.We talk with the center's Karl Schultz about the challenges of programming for Phi--but more specifically, the optimization...
Although Horst Simon was named Deputy Director of Lawrence Berkeley National Laboratory, he maintains his strong ties to the scientific computing community as an editor of the TOP500 list and as an invited speaker at conferences.
Supercomputing veteran, Bo Ewald, has been neck-deep in bleeding edge system development since his twelve-year stint at Cray Research back in the mid-1980s, which was followed by his tenure at large organizations like SGI and startups, including Scale Eight Corporation and Linux Networx. He has put his weight behind quantum company....
May 16, 2013 |
When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
May 15, 2013 |
Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
May 10, 2013 |
Program provides cash awards up to $10,000 for the best open-source end-user applications deployed on 100G network.
May 09, 2013 |
The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system...
May 08, 2013 |
For engineers looking to leverage high-performance computing, the accessibility of a cloud-based approach is a powerful draw, but there are costs that may not be readily apparent.
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.