HPCwire

Since 1986 - Covering the Fastest Computers
in the World and the People Who Run Them

Language Flags

Visit additional Tabor Communication Publications

Datanami
Digital Manufacturing Report
HPC in the Cloud
Green Computing Report

Tabor Communications
Corporate Video

Intel Lifts the Curtain on Larrabee


In a press briefing on Friday, Intel representatives revealed some of the architectural details of the company's much talked-about Larrabee processor. The new design is the chipmaker's first manycore x86 platform and represents what could be described as a general-purpose, x86 vector processor, combining features from both GPUs and CPUs. The architecture is the culmination of more than three years of R&D accomplished under Intel's terascale research program. The company will present a paper at the SIGGRAPH 2008 conference next week in Los Angeles, which will elaborate the design of the processor and its programming model.

The idea behind Larrabee was to jump to the front of the line in GPU programmability, while at the same time deliver an x86 vector processor that can be applied to a wide range of high throughput applications. The new architecture's applicability to visual computing is a result of its general suitability for HPC applications, rather than any GPU-specific capabilities. In fact, Intel characterizes Larrabee as a generic high throughput processor, rather than a GPU. Emphasizing Intel's intentions for the new architecture, Larry Seiler, senior principal engineer on the project said that "Larrabee is going to revolutionize graphics processing and supercomputing."

For the most part, Friday's briefing left out product plans for the new processor. Neither core count, clock speed, nor power consumption was mentioned, and product launch dates were only talked about in the general timeframe of "2009 or 2010." A lot of the discussion focused on Larrabee's role as a high-end GPU for the PC, its initial target market. By entering the high-end volume graphics space, Intel hopes to extend its strong position in the mobile GPU market to desktop gaming.

If it meets with success there, Intel is almost certain to push the platform into the HPC market, where its vector capabilities and x86 compatibility would make it an instant contender against other high-end accelerators like NVIDIA's Tesla products (and other CUDA-supported GPUs), AMD's FireStream GPU offering, Cell processor systems, ClearSpeed co-processors, and even FPGA accelerators. But in Larrabee's case, no external host processor will be required since CPU logic is already on the chip.

Unlike the typical GPU of today, Larrabee has a number of important differences. The overall layout of the chip consists of a number of x86 cores connected to each other via a high speed ring bus, 512 bits wide in each direction. The cores are derived from Intel's Pentium processor, with its short, in-order execution pipelines. In this case though, each core executes up to four threads at a time and contains both a scalar and a vector unit, with the latter able to execute 16 32-bit operations per clock tick. Since Larrabee is basically a CPU architecture, features like context switching, preemptive multitasking, virtual memory and page swapping are built in. And because thread management is done in software, latency can be hidden with conventional parallelization techniques.

Each core contains Level 1 instruction and data caches, with Level 2 cache provided on chip as well. L2 cache is shared between cores, with 256 KB allocated to each one. Unlike GPUs, cache coherency is maintained throughout the cache hierarchy, which enables a software friendly framework for inter-processor communication an efficient mechanism to share data between application threads. Memory controller (or controllers) are on-chip too, as well as application-specific fixed function units.

In general though, a Larrabee processor intended for graphics workload uses very little fixed function hardware. Almost all processing is intended to be performed with software on the x86 cores. In certain cases, notably the texture shader, Intel has added fixed function hardware to boost graphics performance. The rationalization for a mostly graphics software pipeline is that requirements for various functional units (vertex shading, rasterization, pixel shading, etc.) can vary quite a bit from application to application. So workload balancing will be easier to achieve with general-purpose silicon plus software, as opposed to dedicated hardware. That also means that application performance should scale more evenly as additional cores are placed on the die.

To even the playing field in the graphics space, Intel will support DirectX and OpenGL so that existing applications can be ported more easily. A Larrabee-specific API will also be provided for more adventurous programmers who are interested in taking advantage of the full capabilities of the processor. Access to the vector instruction set, which has yet to be described, will be available via C language intrinsics. The vector unit will support IEEE single and double precision floating point operations as well as 32-bit integers.

Even though Larrabee is being characterized as a manycore chip, the first versions will probably have tens of core, rather than the hundreds of cores currently present in the NVIDIA and AMD (ATI) GPUs. Depending on clock speed, Larrabee's raw performance may even be less than that of traditional GPUs. For example, even with the impressive 16 single precision operations per clock (per core), a 1.0 GHz Larrabee chip would need 62 cores to equal the performance of the latest teraflop GPUs from NVIDIA and AMD that will ship this year. Presumably Intel will find the formula to at least match the performance of the competition. But its claim of superior programmability may resonate more than raw performance, especially with software vendors who are looking for more flexibility in developing new types of applications, graphics or otherwise.

Introducing a new architecture into a mature market is always a risky proposition, which Intel itself learned from its Itanium adventure. But the chip vendor is a huge force in the industry and has more than a year to line up ISV and OEM support for Larrabee. Its success in the graphics space will likely determine if the processor becomes a commodity part for HPC. In a way, that's unfortunate, since Larrabee is probably a better fit overall for high-end technical computing than for the more narrow domain of visual computing. Either way, the competition among Intel, AMD and NVIDIA is bound to get more interesting.

June 19, 2013

June 18, 2013

June 17, 2013

June 14, 2013

June 13, 2013

June 12, 2013

June 11, 2013

June 10, 2013

June 07, 2013

June 06, 2013


Most Read Features

Most Read Around the Web

Most Read This Just In

Asetek

Short Takes

Supercomputers: Not Always the Best for Big Data

Jun 18, 2013 | The world's largest supercomputers, like Tianhe-2, are great at traditional, compute-intensive HPC workloads, such as simulating atomic decay or modeling tornados. But data-intensive applications--such as mining big data sets for connections--is a different sort of workload, and runs best on a different sort of computer.
Read more...

Gordon Flashes Its Versatility in HPC Workloads

Jun 18, 2013 | Researchers are finding innovative uses for Gordon, the 285 teraflop supercomputer housed at the San Diego Supercomputer Center (SDSC) that has a unique Flash-based storage system. Since going online, researchers have put the incredibly fast I/O to use on a wide variety of workloads, ranging from chemistry to political science.
Read more...

Supercomputers: Still the King of the HPC Hill

Jun 17, 2013 | The advent of low-power mobile processors and cloud delivery models is changing the economics of computing. But just as an economy car is good at different things than a full size truck, an HPC workload still has certain computing demands that neither the fastest smartphone nor the most elastic cloud cluster can fulfill.
Read more...

TACC Longhorn Takes On Natural Language Processing

Jun 14, 2013 | For all the progress we've made in IT over the last 50 years, there's one area of life that has steadfastly eluded the grasp of computers: understanding human language. Now, researchers at the Texas Advanced Computing Center (TACC) are utilizing a Hadoop cluster on its Longhorn supercomputer to move the state of the art of language processing a little bit further.
Read more...

Titan Didn't Redo LINPACK for June Top 500 List

Jun 13, 2013 | Titan, the Cray XK7 at the Oak Ridge National Lab that debuted last fall as the fastest supercomputer in the world with 17.59 petaflops of sustained computing power, will rely on its previous LINPACK test for the upcoming edition of the Top 500 list.
Read more...

Sponsored Whitepapers

Best Practices in Big Data Storage

05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.

Progress in Parallel: the Bull Parallel Programming Center

04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.

Sponsored Multimedia

HPCwire Live! Atlanta's Big Data Kick Off Week Meets HPC

Join HPCwire Editor Nicole Hemsoth and Dr. David Bader from Georgia Tech as they take center stage on opening night at Atlanta's first Big Data Kick Off Week, filmed in front of a live audience. Nicole and David look at the evolution of HPC, today's big data challenges, discuss real world solutions, and reveal their predictions. Exactly what does the future holds for HPC?

Webinar: Mellanox Virtual Modular Switch, the Most Efficient 40GbE Aggregation Switch Solution

Join our webinar to learn how IT managers can migrate to a more resilient, flexible and scalable solution that grows with the data center. Mellanox VMS is future-proof, efficient and brings significant CAPEX and OPEX savings. The VMS is available today.

Atlanta's Big Data Kick Off Week Meets HPC Cray

HPC Job Bank


Featured Events






  • November 17, 2013 - November 22, 2013
    SC'13
    Denver, CO
    United States


HPCwire Events