Visit additional Tabor Communication Publications
November 13, 2008
Barcelona, we hardly knew ye. Today AMD launched its 45nm "Shanghai" quad-core Opterons, sending the ill-fated 65nm Barcelona chips into the microprocessor history books. While the company has some catching up to do with regard to Intel hardware, AMD is counting on its newly shrunk processor line to regain some lost market share from its rival. Intel has had 45nm parts on the market for a year, which has chipped away at AMD's customer base. AMD decided to lead its 45nm charge with its server lineup, leaving the corresponding mobile and desktop products for Q1 2009.
Immediately available will be the 75W versions of Shanghai, at speeds of 2.3 to 2.7 GHz. In Q1 2009, the HE (55W) and SE (105W) versions will hit the channel. The high-performance SE chips should be of special interest to the HPC crowd, but AMD hasn't yet divulged the clock speed, other than to say it will be somewhere north of 2.7 GHz. The entire line is compatible with the Rev F socket, so the new chips can be plugged into existing machines with just a BIOS upgrade.
As you might guess from a process shrink, the new CPUs will run at higher clock frequencies (up to 2.7 GHz), have more cache (8 GB), and deliver better performance/watt (great taste/less filling). AMD is claiming up to 35 percent better performance and 35 percent less power consumption at idle. The new chips also support faster DDR2 memory (800 MHz), which delivers 10 percent more bandwidth than the previous controller. An interesting new feature is the "Smart Fetch" technology, where cores automatically power down when waiting for data or instructions to arrive after some threshold time is exceeded. The cores dumps their local L1 and L2 cache to L3 before going to sleep, reversing the process upon waking up.
The Shanghai parts are being produced with a new 45nm immersion lithography process. AMD says the technology yields a tighter projection beam, which supports more precise geometry and leads to less manufacturing defects. According to Steve Demski, AMD's product manager for the Server and Workstation Division, this has a distinct cost advantage over the double-etch manufacture technology being used by Intel. It also enabled AMD to transition relatively rapidly to the new manufacturing node. "This has been the quickest process for any Opteron processors we've developed," Demski told me.
According to him, AMD moved up the launch of the Shanghai chips about three months, which he said was originally slated for Q1 2009. My recollection from last year is that AMD promised 45nm parts in the middle of 2008, which I always thought was a long shot. Certainly Intel's success with its 45nm Harpertown chips motivated AMD to push out its Opteron contender as quickly as possible. The original plan was to build HyperTransport 3.0 into Shanghai for faster (17.6 GB/s) chip-to-chip communication, but collapsing the product timeline meant it had to stick with slower HT 1.0 for the initial launch. In Q2 2009, all the Shanghai chips will move to HT 3.0, at which point AMD will also bump the clock speed across the different power bands.
Shanghai is being positioned against Intel's Harpertown (5400 series) processors. According to AMD, the new chips match the comparable Harpertowns on integer performance (SPECint_rate2006) and are about 34 percent better on floating point (SPECfp_rate2006), while memory bandwidth is nearly twice as good. Shanghai will almost certainly provide better energy efficiency than their Intel competition because of the use of power-hungry FB-DIMMs in Harpertown-based systems.
And since the 5400s use the older front-side-bus technology, AMD can still exploit the advantages of its on-chip memory controllers and HyperTransport/Direct Connect Architecture, but this will be the last time it will be able to do so. Early next year, Intel is expected to launch its first Nehalem server parts, which will incorporate on-chip memory controllers and a HyperTransport-like QuickPath Interconnect (QPI). AMD intends to answer Nehalem with its 6-core "Istanbul" processor toward the latter half of 2009, which will also be socket compatible with Rev F.
Of course, this is a tough business climate to be launching new products, given that it's the end of capitalism and all. And AMD is probably resigned to the fact that Nehalem will outperform the Shanghai, and perhaps even Istanbul. But in speaking with Demski, it sounded like AMD was hoping the recession might actually help the company's message in the server market. The theory is that customers would be more likely to plug faster Opteron processors into existing systems than perform an expensive forklift upgrade, as will be required for the new Nehalem-based machines. AMD was apparently spreading this talking point around. Over at InfoWorld, Tom Yager writes:
Intel's messaging is all about the future, but AMD takes an interesting view that's more in line with the perspective of buyers: Squeeze the longest possible life out of the gear you bought two years ago, and keep the machine you buy today upgradable to state-of-the-art performance with nothing but a CPU swap.
It's certainly a reasonable line of thinking, but the fact is that neither chipmaker is likely to have a good fourth quarter, or a good 2009. Intel recently cut its forecast for Q4 noting that "revenue is being affected by significantly weaker-than-expected demand in all geographies and market segments." That reflects this week's IDC report in which it cut its previous IT spending forecast in half -- from 5.9 percent to 2.6 percent.
So both chipmakers are likely to shed workers over the next 12 months. Even if the HPC segment remains strong during the recession, the upshot of R&D cutbacks at Intel, AMD and other big players will likely slow product innovation and development, which could have longer term effects on high performance computing.
Posted by Michael Feldman - November 12, 2008 @ 9:00 PM, Pacific Standard Time
Michael Feldman is the editor of HPCwire.
No Recent Blog Comments
In a recent solicitation, the NSF laid out needs for furthering its scientific and engineering infrastructure with new tools to go beyond top performance, Having already delivered systems like Stampede and Blue Waters, they're turning an eye to solving data-intensive challenges. We spoke with the agency's Irene Qualters and Barry Schneider about..
Large-scale, worldwide scientific initiatives rely on some cloud-based system to both coordinate efforts and manage computational efforts at peak times that cannot be contained within the combined in-house HPC resources. Last week at Google I/O, Brookhaven National Lab’s Sergey Panitkin discussed the role of the Google Compute Engine in providing computational support to ATLAS, a detector of high-energy particles at the Large Hadron Collider (LHC).
The Xeon Phi coprocessor might be the new kid on the high performance block, but out of all first-rate kickers of the Intel tires, the Texas Advanced Computing Center (TACC) got the first real jab with its new top ten Stampede system.We talk with the center's Karl Schultz about the challenges of programming for Phi--but more specifically, the optimization...
May 22, 2013 |
At some point in the not-too-distant future, building powerful, miniature computing systems will be considered a hobby for high schoolers, just as robotics or even Lego-building are today. That could be made possible through recent advancements made with the Raspberry Pi computers.
May 16, 2013 |
When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
May 15, 2013 |
Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
May 10, 2013 |
Program provides cash awards up to $10,000 for the best open-source end-user applications deployed on 100G network.
May 09, 2013 |
The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system...
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.