Visit additional Tabor Communication Publications
December 18, 2008
Joint collaboration aims to deliver complete design flow for the 32-nm process
MOUNTAIN VIEW, Calif., Dec. 18 -- Synopsys, Inc., a world leader in software and IP for semiconductor design and manufacturing, today announced early results of its 32-nanometer (nm)-centric joint collaboration with STMicroelectronics, a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications. The two companies have a close ongoing collaboration to establish all the necessary components for a successful 32-nm design flow, including STMicroelectronics' leading-edge standard cell library for low power and high-performance design, and the support of the latest route rules in Synopsys' IC Compiler Zroute technology. Zroute's unique architecture and state-of-the-art routing algorithms are important to meeting the 32-nm technology requirements while delivering the best quality of results.
The collaboration makes STMicroelectronics the first company to pre- qualify and deliver state-of-the-art libraries internally for the high-k metal gate 32-nm low power International Semiconductor Development Alliance (ISDA) process, based on Synopsys' IC Compiler. This has enabled STMicroelectronics to begin implementing a complex Digital Signal Processor (DSP) core test chip, which in turn will allow validation-in-silicon to be carried out on a complete set of low power solutions for the ISDA process in the second half of 2009.
"As a joint development partner of the ISDA, STMicroelectronics stays at the forefront of advanced process technology development," said Philippe Magarshack, group vice president at STMicroelectronics' Technology Research and Development (R&D). "Since early on, we have worked closely with Synopsys to enable the readiness of key components in our 32-nm design flow. Synopsys' ability to quickly support the evolving 32-nm route rules in IC Compiler's Zroute technology enabled us to validate our standard cell library routability and optimize it for the highest density. The availability of the first standard cell library is a key achievement towards 32-nm readiness."
For library development, STMicroelectronics used the Synopsys Cadabra product. For route rule development, the chosen vehicle was Zroute technology in Synopsys' IC Compiler, developed from the ground up to address emerging design and design-for-manufacturing (DFM) challenges at advanced process nodes. Zroute's unique architecture can support advanced design rules and at the same time meet aggressive performance targets. In addition, Zroute's native multi- threading support takes advantage of the latest multi-core computing systems to deliver near-linear scalability of runtimes. For extraction and time analysis of the library, STMicroelectronics is using Synopsys' Star-RCXTTM and PrimeTime golden signoff tools.
"STMicroelectronics has been a long time, valued customer, actively collaborating in new technology development to help guide the direction of our products," said Antun Domic, senior vice president and general manager of Synopsys' Implementation Group. "The latest achievements in 32-nm design enablement are examples of our close collaboration bearing fruit. Zroute technology in IC Compiler provides a critical component at the right time to meet the needs of the 32-nm transition. We are committed to continuing our collaboration with STMicroelectronics towards the final objective of a production-ready environment for high-quality 32-nm design."
Synopsys, Inc. is the world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design and manufacturing. Synopsys' comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and field-programmable gate array (FPGA) solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, software-to-silicon verification and time-to-results. These technology-leading solutions help give Synopsys customers a competitive edge in bringing the best products to market quickly while reducing costs and schedule risk. Synopsys is headquartered in Mountain View, Calif., and has more than 60 offices located throughout North America, Europe, Japan, Asia and India. Visit Synopsys online at http://www.synopsys.com/.
SOURCE: Synopsys, Inc.
In quieter times, sounding the bell of funding big science with big systems tends to resonate further than when ears are already burning with sour economic and national security news. For exascale's future, however, the time could be ripe to instill some sense of urgency....
In a recent solicitation, the NSF laid out needs for furthering its scientific and engineering infrastructure with new tools to go beyond top performance, Having already delivered systems like Stampede and Blue Waters, they're turning an eye to solving data-intensive challenges. We spoke with the agency's Irene Qualters and Barry Schneider about..
Large-scale, worldwide scientific initiatives rely on some cloud-based system to both coordinate efforts and manage computational efforts at peak times that cannot be contained within the combined in-house HPC resources. Last week at Google I/O, Brookhaven National Lab’s Sergey Panitkin discussed the role of the Google Compute Engine in providing computational support to ATLAS, a detector of high-energy particles at the Large Hadron Collider (LHC).
May 23, 2013 |
The study of climate change is one of those scientific problems where it is almost essential to model the entire Earth to attain accurate results and make worthwhile predictions. In an attempt to make climate science more accessible to smaller research facilities, NASA introduced what they call ‘Climate in a Box,’ a system they note acts as a desktop supercomputer.
May 22, 2013 |
At some point in the not-too-distant future, building powerful, miniature computing systems will be considered a hobby for high schoolers, just as robotics or even Lego-building are today. That could be made possible through recent advancements made with the Raspberry Pi computers.
May 16, 2013 |
When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
May 15, 2013 |
Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.