Visit additional Tabor Communication Publications
August 03, 2010
Although "Bulldozer" CPUs won't be hitting the streets until next year, AMD is already cranking up the marketing machinery for the new chip. In the first of a series of blogs devoted entirely to the new microarchitecture, John Fruehe, AMD's director of product marketing for the server/workstation products, tells us we should expect to see details of the new processor to roll out throughout the rest of the year. AMD first previewed Bulldozer back in November 2009, and according to Fruehe, the design will be presented at the upcoming Hot Chips 22 conference on August 24th.
Bulldozer represents a revamped multicore architecture for AMD's high end CPUs, and will be will be the basis of the company's Opteron and top-of-the line client CPUs in 2011. Fruehe summed up the processor thusly:
Just to make sure that everyone is up to speed on what Bulldozer is — a brand new design featuring up to 8 cores for client products and up to 16 cores for server products. Bulldozer will feature a new floating point unit that can support up to 256-bit floating point execution, which will boost the performance for technical applications that rely on floating point math.
Interlagos, the 16-core sequel to AMD's Magny-Cours Opteron, will be a Bulldozer design and will be produced on the 32nm process node. As such, it will pitted against Intel's Sandy Bridge microarchitecture, also slated to show up in 2011.
Full story at The Bulldozer Blog
Large-scale, worldwide scientific initiatives rely on some cloud-based system to both coordinate efforts and manage computational efforts at peak times that cannot be contained within the combined in-house HPC resources. Last week at Google I/O, Brookhaven National Lab’s Sergey Panitkin discussed the role of the Google Compute Engine in providing computational support to ATLAS, a detector of high-energy particles at the Large Hadron Collider (LHC).
The Xeon Phi coprocessor might be the new kid on the high performance block, but out of all first-rate kickers of the Intel tires, the Texas Advanced Computing Center (TACC) got the first real jab with its new top ten Stampede system.We talk with the center's Karl Schultz about the challenges of programming for Phi--but more specifically, the optimization...
Although Horst Simon was named Deputy Director of Lawrence Berkeley National Laboratory, he maintains his strong ties to the scientific computing community as an editor of the TOP500 list and as an invited speaker at conferences.
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.