As part of this week’s International Solid State Circuits Conference (ISSCC) in San Francisco, AMD is releasing details about the upcoming Bulldozer chip. AMD Fellow Tim Fischer covers the highlights in a blog post.
Fischer writes:
To quickly review, the centerpiece of the “Bulldozer” module is its two tightly-linked processor cores (Figure 1). These cores share several high-bandwidth resources (such as the Floating Point Unit) to provide chip-multithreading (CMT) which efficiently executes multiple instruction threads in parallel. Bulldozer’s CMT provides a marked design improvement over current threading approaches which either funnel multiple instruction threads through one processor core (SMT) or replicate cores statically (CMP) — approaches with inherent constraints and performance bottlenecks.
Fischer goes on to explain that Bulldozers’s silicon circuit design uses GlobalFoundries’ advanced 32nm Silicon-on-Insulator (SOI) process “to provide significant advantages in power, performance, and reliability.” The chip’s core circuit design is the subject of an ISSCC paper (Session 4.5) titled “Design Solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU”.
According to Fischer, the paper will cover “changes in clocking, latching, power management and on-chip memories…along with significant power reduction improvements, including clock gating, a new low-power flop design, and L1 cache power improvements.”
Also released were details on Bulldozer’s Floating Point Unit (FPU), which was designed to enhance the chip’s performance while reducing energy demands:
High performance computing relies heavily on vector (packed integer) and floating point operations, both handled in the FPU. Bulldozer was designed to execute these operations at higher performance and using less power than the current generation of microprocessors. Key to Bulldozer’s performance and power improvements are FPU changes, including completely redesigned arithmetic units and control structures. …As previously described at HotChips 2010, the Bulldozer FPU supports new instructions including SSSE3, SSE4.1, SSE4.2, AVX, AES, and advanced Multiply-Add/Accumulate operations.
Another ISSCC paper (Session 4.6) titled “40-entry Unified, Out-of-Order Scheduler and Integer Execution Unit for the AMD Bulldozer x86-64 Core” covers the changes made to the Integer Execution Unit.