Visit additional Tabor Communication Publications
March 03, 2011
NVIDIA's unveiling of Project Denver in January 2011 certainly portends big changes ahead for the GPU maker. Over the next couple of years, it will attempt to turn itself from a graphics chip vendor into a computing company. But to make it work, NVIDIA will have to do something no other company has been able to do: take a big chunk of Intel's volume x86 business.
To recap, Project Denver is NVIDIA's initiative to build high-end heterogeneous processors, integrating custom-built ARM CPUs with GPUs. The resulting chips are destined for workstations, servers and supercomputers. The brawnier Denver parts will parallel the company's Tegra line, NVIDIA's mobile processors that have already successfully delivered ARM CPU-GPU processors into the marketplace.
The Denver strategy is familiar: leverage essentially the same processor designs across an entire product portfolio. NVIDIA's plan is that in two or three years, the chip they deliver for a smartphone will be a baby brother to the one delivered for a supercomputer. It's the same model Intel has successfully employed for decades with its x86 architecture.
The emergence of commodity x86 clusters in the 1990s, aka Attack of the Killer Micros, was based on the fact that Intel and AMD could leverage their PC business into the server space. Since the high-end Xeons and Opterons are just souped-up versions of their mainstream x86 design, R&D and production costs can be spread across the entire enterprise. It could be argued that the eventual failure of Intel's Itanium CPU in the HPC space was the result of that architecture's lack of a volume market, i.e., from a performance-per-dollar perspective, the hardware became too expensive to deploy at the scale of a supercomputer.
It's no secret that for the past couple of decades the desktop computer business has subsidized the x86 server business. NVIDIA is taking advantage of this same model; in this case, using the gaming market for GPUs to subsidize its Tesla HPC business. It's hard to imagine either the Xeon or Tesla business could exist on its own.
But the consumer market is now shifting. In particular, the personal computer business is moving from the desktop to mobile devices like smartphones and tablets, and for the most part, these are ARM-based platforms. And since these mobile devices are more numerous than desktop/laptop systems (and in some cases are replacing them), the ARM CPU now has the advantage in volume.
As I wrote in a recent report on the future of ARM architecture in HPC:
When total shipments are considered, ARM outruns x86 by about a 10-to-1 margin. In 2010, more than 6 billion ARM-based processors were sold, and that number is projected to grow to 8 or 9 billion over the next three years.
Intel's problem is not just that x86 consumer devices will shift to ARM, but as a result of the volume disruption, the economics of Intel's higher margin x86 server and workstation business will be threatened as well. That is certainly what NVIDIA is counting on, at least to some degree.
Ars Technica's Jon Stokes provides an interesting analysis of how this could play out. He begins by arguing that NVIDIA ARM chips will lose the performance and the performance/watt battle with Intel silicon:
First, there's simply no way that any ARM CPU vendor, NVIDIA included, will even approach Intel's desktop and server x86 parts in terms of raw performance any time in the next five years, and probably not in this decade. Intel will retain its process leadership, and Xeon will retain the CPU performance crown. Per-thread performance is a very, very hard problem to solve, and Intel is the hands-down leader here.
It's also the case that as ARM moves up the performance ladder, it will necessarily start to drop in terms of power efficiency. Again, there is no magic pixie dust here, and the impact of the ISA alone on power consumption in processors that draw many tens of watts is negligible. A multicore ARM chip and a multicore Xeon chip that give similar performance on compute-intensive workloads will have similar power profiles; to believe otherwise is to believe in magical little ARM performance elves.
In the case of pure CPU thread performance, Stokes may indeed be right about Intel winning that race. But he seems to have forgotten that NVIDIA will have GPUs on-chip as well. I've got to believe that NVIDIA expects its GPU, and not the ARM unit, to do the heavy-duty number crunching on its processors. Certainly for most HPC and visual computing applications, the graphics engine will be the workhorse.
Also for many (most?) compute-intensive applications that must be confined to a CPU, multi-threaded performance is much more important than single-threaded performance. Certainly if you can keep all the cores fed with data, it's better to go with less performant cores if you can simply provide more of them, as AMD is doing with its latest Opterons.
For the same reason, I think Stokes' power efficiency argument is overstated. Right now ARM designs are more energy efficient than x86 designs, mainly because the former is a simpler architecture. While future 64-bit ARM designs will almost certainly be more complex that their 32-bit counterparts, there's little reason to believe that they'll need to be as complex as say a Xeon. It remains to be seen how NVIDIA will balance performance and energy efficiency in their future Denver design.
Despite Stokes' misgivings about ARM's performance prospects, he still believes Intel and the x86 are in for a rough time -- mainly for the same volume economic drivers I talked about earlier. In fact, he speculates that Intel might be forced to develop its own ARM CPU line or open up its fabs to ARM-based SoCs. Of course, AMD could also get into the ARM business, and perhaps has an even greater incentive to do so given its lack of a viable CPU for the mobile space.
Of course the x86 has proved to be remarkably resilient to competing architectures -- PowerPC, MIPS, SPARC, Itanium, to name a few. And even though on paper the ARM numbers look overwhelming, the CPU business is not a board game. As with many things, you often can't tell how much momentum something has until you try to stop it.
Posted by Michael Feldman - March 03, 2011 @ 6:16 PM, Pacific Standard Time
Michael Feldman is the editor of HPCwire.
No Recent Blog Comments
Large-scale, worldwide scientific initiatives rely on some cloud-based system to both coordinate efforts and manage computational efforts at peak times that cannot be contained within the combined in-house HPC resources. Last week at Google I/O, Brookhaven National Lab’s Sergey Panitkin discussed the role of the Google Compute Engine in providing computational support to ATLAS, a detector of high-energy particles at the Large Hadron Collider (LHC).
The Xeon Phi coprocessor might be the new kid on the high performance block, but out of all first-rate kickers of the Intel tires, the Texas Advanced Computing Center (TACC) got the first real jab with its new top ten Stampede system.We talk with the center's Karl Schultz about the challenges of programming for Phi--but more specifically, the optimization...
Although Horst Simon was named Deputy Director of Lawrence Berkeley National Laboratory, he maintains his strong ties to the scientific computing community as an editor of the TOP500 list and as an invited speaker at conferences.
May 16, 2013 |
When it comes to cloud, long distances mean unacceptably high latencies. Researchers from the University of Bonn in Germany examined those latency issues of doing CFD modeling in the cloud by utilizing a common CFD and its utilization in HPC instance types including both CPU and GPU cores of Amazon EC2.
May 15, 2013 |
Supercomputers at the Department of Energy’s National Energy Research Scientific Computing Center (NERSC) have worked on important computational problems such as collapse of the atomic state, the optimization of chemical catalysts, and now modeling popping bubbles.
May 10, 2013 |
Program provides cash awards up to $10,000 for the best open-source end-user applications deployed on 100G network.
May 09, 2013 |
The Japanese government has revealed its plans to best its previous K Computer efforts with what they hope will be the first exascale system...
05/10/2013 | Cleversafe, Cray, DDN, NetApp, & Panasas | From Wall Street to Hollywood, drug discovery to homeland security, companies and organizations of all sizes and stripes are coming face to face with the challenges – and opportunities – afforded by Big Data. Before anyone can utilize these extraordinary data repositories, however, they must first harness and manage their data stores, and do so utilizing technologies that underscore affordability, security, and scalability.
04/15/2013 | Bull | “50% of HPC users say their largest jobs scale to 120 cores or less.” How about yours? Are your codes ready to take advantage of today’s and tomorrow’s ultra-parallel HPC systems? Download this White Paper by Analysts Intersect360 Research to see what Bull and Intel’s Center for Excellence in Parallel Programming can do for your codes.
In this demonstration of SGI DMF ZeroWatt disk solution, Dr. Eng Lim Goh, SGI CTO, discusses a function of SGI DMF software to reduce costs and power consumption in an exascale (Big Data) storage datacenter.
The Cray CS300-AC cluster supercomputer offers energy efficient, air-cooled design based on modular, industry-standard platforms featuring the latest processor and network technologies and a wide range of datacenter cooling requirements.